#******************************************************************************
# Triggers.rbm
#
# (c) Copyright 2011
# National Instruments Corporation.
# All rights reserved.
# License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT
# Refer to "MHDDK License Agreement.pdf" in the root of this distribution.
#
# Description:
# rbm file for Triggers.
# This file is autogenerated. Do not modify it directly.
#
# All lines starting with # or C are comments
# All lines starting with T define a register Type
# All lines starting with TR define register name, type, offset
# All lines starting with F are Fields within the preceding register,
# Its name, size, attribute (Strobe|.) and type are defined.
#
#******************************************************************************
# Declaring RBM as a containable chip object.
# This means all instances must specify an offset for it.
--containable
--generate-include "tTriggersValues.h"
#===============================================================================
# Register Group Enumerated_Types
#===============================================================================
#-------------------------------------------------------------------------------
# Enumerated type PFI_WDT_Mode_t
#-------------------------------------------------------------------------------
E PFI_WDT_Mode_t
V WdtMode_Disabled 0
V WdtMode_Freeze 1
V WdtMode_Tristate 2
V WdtMode_SafeValue 3
#-------------------------------------------------------------------------------
# Enumerated type TrigPllLockedStatus_t
#-------------------------------------------------------------------------------
E TrigPllLockedStatus_t
V PLL_NotLocked 0
V PLL_Locked 1
#-------------------------------------------------------------------------------
# Enumerated type Trig_Analog_Trigger_Mode_t
#-------------------------------------------------------------------------------
E Trig_Analog_Trigger_Mode_t
V ATrigMode_Low_Window 0
V ATrigMode_High_Window 1
V ATrigMode_Middle_Window 2
V ATrigMode_High_Hysteresis 4
V ATrigMode_Low_Hysteresis 6
#-------------------------------------------------------------------------------
# Enumerated type Trig_Atrig_Sel_t
#-------------------------------------------------------------------------------
E Trig_Atrig_Sel_t
V ATrigSel_AI_Chan 0
V ATrigSel_APFI0 1
V ATrigSel_APFI1 2
V ATrigSel_Ground 3
#-------------------------------------------------------------------------------
# Enumerated type Trig_FOUT_Enable_t
#-------------------------------------------------------------------------------
E Trig_FOUT_Enable_t
V FOUT_Disabled 0
V FOUT_Enabled 1
#-------------------------------------------------------------------------------
# Enumerated type Trig_FOUT_FastTB_DivideBy2_t
#-------------------------------------------------------------------------------
E Trig_FOUT_FastTB_DivideBy2_t
V FOUT_FastTB_isTB1 0
V FOUT_FastTB_isTB1_DivBy2 1
#-------------------------------------------------------------------------------
# Enumerated type Trig_FOUT_Timebase_Select_t
#-------------------------------------------------------------------------------
E Trig_FOUT_Timebase_Select_t
V FOUT_Src_IsFastTB 0
V FOUT_Src_IsTB2 1
#-------------------------------------------------------------------------------
# Enumerated type Trig_Filter_Custom_Timebase_t
#-------------------------------------------------------------------------------
E Trig_Filter_Custom_Timebase_t
V Filter_Timebase_TB3 0
V Filter_Timebase_TB2 1
V External_Signal 2
#-------------------------------------------------------------------------------
# Enumerated type Trig_Filter_Ext_Signal_Select_t
#-------------------------------------------------------------------------------
E Trig_Filter_Ext_Signal_Select_t
V Filter_Ext_Signal_IntTriggerA0 0
V Filter_Ext_Signal_IntTriggerA1 1
V Filter_Ext_Signal_IntTriggerA2 2
V Filter_Ext_Signal_IntTriggerA3 3
V Filter_Ext_Signal_IntTriggerA4 4
V Filter_Ext_Signal_IntTriggerA5 5
V Filter_Ext_Signal_IntTriggerA6 6
V Filter_Ext_Signal_IntTriggerA7 7
#-------------------------------------------------------------------------------
# Enumerated type Trig_Filter_Select_t
#-------------------------------------------------------------------------------
E Trig_Filter_Select_t
V No_Filter 0
V Sync_To_TB3 1
V Small_Filter 2
V Medium_Filter 3
V Large_Filter 4
V Custom_Filter_1 5
V Custom_Filter_2 6
#-------------------------------------------------------------------------------
# Enumerated type Trig_IntTriggerA_i_Output_Select_t
#-------------------------------------------------------------------------------
E Trig_IntTriggerA_i_Output_Select_t
V IntTriggerA_PFI0 0
V IntTriggerA_PFI1 1
V IntTriggerA_PFI2 2
V IntTriggerA_PFI3 3
V IntTriggerA_PFI4 4
V IntTriggerA_PFI5 5
V IntTriggerA_PFI6 6
V IntTriggerA_PFI7 7
V IntTriggerA_PFI8 8
V IntTriggerA_PFI9 9
V IntTriggerA_PFI10 10
V IntTriggerA_PFI11 11
V IntTriggerA_PFI12 12
V IntTriggerA_PFI13 13
V IntTriggerA_PFI14 14
V IntTriggerA_PFI15 15
V IntTriggerA_RTSI0 16
V IntTriggerA_RTSI1 17
V IntTriggerA_RTSI2 18
V IntTriggerA_RTSI3 19
V IntTriggerA_RTSI4 20
V IntTriggerA_RTSI5 21
V IntTriggerA_RTSI6 22
V IntTriggerA_RTSI7 23
V IntTriggerA_PXI_StarTrig 32
V IntTriggerA_PXIe_DStarA 33
V IntTriggerA_PXIe_DStarB 34
V IntTriggerA_ReferenceClock 35
V IntTriggerA_FOUT 36
V IntTriggerA_ATrig 37
V IntTriggerA_AI_CONVERT 38
V IntTriggerA_AI_START 39
V IntTriggerA_AI_START1 40
V IntTriggerA_AI_START2 41
V IntTriggerA_AI_Gate 42
V IntTriggerA_DI_Convert 43
V IntTriggerA_DI_Start1 44
V IntTriggerA_DI_Start2 45
V IntTriggerA_DI_Gate 46
V IntTriggerA_AO_UPDATE 55
V IntTriggerA_AO_START1 56
V IntTriggerA_AO_Gate 57
V IntTriggerA_DO_Update 58
V IntTriggerA_DO_Start1 59
V IntTriggerA_DO_Gate 60
V IntTriggerA_DIO_ChangeDetect 61
V IntTriggerA_G0_SRC 62
V IntTriggerA_G0_GATE 63
V IntTriggerA_G0_OUT 64
V IntTriggerA_G0_SampleClk 65
V IntTriggerA_G1_SRC 66
V IntTriggerA_G1_GATE 67
V IntTriggerA_G1_OUT 68
V IntTriggerA_G1_SampleClk 69
V IntTriggerA_G2_SRC 70
V IntTriggerA_G2_GATE 71
V IntTriggerA_G2_OUT 72
V IntTriggerA_G2_SampleClk 73
V IntTriggerA_G3_SRC 74
V IntTriggerA_G3_GATE 75
V IntTriggerA_G3_OUT 76
V IntTriggerA_G3_SampleClk 77
V IntTriggerA_WatchdogExpiredPulse 78
V IntTriggerA_G0_HwArm 103
V IntTriggerA_G1_HwArm 104
V IntTriggerA_G2_HwArm 105
V IntTriggerA_G3_HwArm 106
#-------------------------------------------------------------------------------
# Enumerated type Trig_PFI_Output_Select_t
#-------------------------------------------------------------------------------
E Trig_PFI_Output_Select_t
V PFI_WatchdogExpired 0
V PFI_AI_Start1 1
V PFI_AI_Start2 2
V PFI_AI_Convert 3
V PFI_G1_SRC 4
V PFI_G1_Gate 5
V PFI_AO_Update 6
V PFI_AO_Start1 7
V PFI_AI_Start 8
V PFI_G0_SRC 9
V PFI_G0_Gate 10
V PFI_SCXI_SpiClk 11
V PFI_AI_ExternalMux_Clk 12
V PFI_G0_Out 13
V PFI_G1_Out 14
V PFI_Freq_Out 15
V PFI_DO 16
V PFI_Atrig 17
V PFI_RTSI0 18
V PFI_RTSI1 19
V PFI_RTSI2 20
V PFI_RTSI3 21
V PFI_RTSI4 22
V PFI_RTSI5 23
V PFI_RTSI6 24
V PFI_RTSI7 25
V PFI_Star_Trig 26
V PFI_SCXI_Trig1_in 27
V PFI_DIO_Change_Detect 28
V PFI_DI_Convert 29
V PFI_DO_Update 30
V PFI_G2_SRC 31
V PFI_G2_Gate 32
V PFI_G2_Out 33
V PFI_G3_SRC 34
V PFI_G3_Gate 35
V PFI_G3_Out 36
V PFI_DO_Start1 37
V PFI_DO_Gate 38
V PFI_DI_Start1 39
V PFI_DI_Start2 40
V PFI_DI_Gate 41
V PFI_PXIe_DStarA 42
V PFI_PXIe_DStarB 43
V PFI_G0_SampleClk 44
V PFI_G1_SampleClk 45
V PFI_G2_SampleClk 46
V PFI_G3_SampleClk 47
V PFI_AI_Gate 56
V PFI_AO_Gate 57
V PFI_IntTriggerA0 66
V PFI_IntTriggerA1 67
V PFI_IntTriggerA2 68
V PFI_IntTriggerA3 69
V PFI_IntTriggerA4 70
V PFI_IntTriggerA5 71
V PFI_IntTriggerA6 72
V PFI_IntTriggerA7 73
V PFI_G0_HwArm 74
V PFI_G1_HwArm 75
V PFI_G2_HwArm 76
V PFI_G3_HwArm 77
#-------------------------------------------------------------------------------
# Enumerated type Trig_PFI_i_Pin_Dir_t
#-------------------------------------------------------------------------------
E Trig_PFI_i_Pin_Dir_t
V PFI_Input 0
V PFI_Output 1
#-------------------------------------------------------------------------------
# Enumerated type Trig_PLL_Filter_Range_t
#-------------------------------------------------------------------------------
E Trig_PLL_Filter_Range_t
V PLL_100MHz 6
#-------------------------------------------------------------------------------
# Enumerated type Trig_PLL_In_Source_Select_t
#-------------------------------------------------------------------------------
E Trig_PLL_In_Source_Select_t
V RefClkSrc_PXIe_Clk100 1
V RefClkSrc_PXIe_DStarA 2
V RefClkSrc_PXIe_DStarB 3
V RefClkSrc_Star_Trigger 4
V RefClkSrc_RTSI0 5
V RefClkSrc_RTSI1 6
V RefClkSrc_RTSI2 7
V RefClkSrc_RTSI3 8
V RefClkSrc_RTSI4 9
V RefClkSrc_RTSI5 10
V RefClkSrc_RTSI6 11
V RefClkSrc_RTSI7 12
V RefClkSrc_PFI0 13
V RefClkSrc_PFI1 14
V RefClkSrc_PFI2 15
V RefClkSrc_PFI3 16
V RefClkSrc_PFI4 17
V RefClkSrc_PFI5 18
V RefClkSrc_PFI6 19
V RefClkSrc_PFI7 20
V RefClkSrc_PFI8 21
V RefClkSrc_PFI9 22
V RefClkSrc_PFI10 23
V RefClkSrc_PFI11 24
V RefClkSrc_PFI12 25
V RefClkSrc_PFI13 26
V RefClkSrc_PFI14 27
V RefClkSrc_PFI15 28
#-------------------------------------------------------------------------------
# Enumerated type Trig_RTSI_i_Output_Select_t
#-------------------------------------------------------------------------------
E Trig_RTSI_i_Output_Select_t
V RTSI_AI_START1 0
V RTSI_AI_START2 1
V RTSI_AI_CONVERT 2
V RTSI_AO_UPDATE 3
V RTSI_AO_START1 4
V RTSI_G0_SRC 5
V RTSI_G0_GATE 6
V RTSI_G0_OUT 7
V RTSI_G0_Z 8
V RTSI_AO_Gate 9
V RTSI_AI_Gate 10
V RTSI_FOUT 11
V RTSI_RefClkOut 12
V RTSI_DIO_ChangeDetect 13
V RTSI_WatchdogExpiredPulse 14
V RTSI_PFI0 15
V RTSI_PFI1 16
V RTSI_PFI2 17
V RTSI_PFI3 18
V RTSI_PFI4 19
V RTSI_PFI5 20
V RTSI_G1_OUT 21
V RTSI_G1_GATE 22
V RTSI_G1_SRC 23
V RTSI_G1_Z 24
V RTSI_Atrig 25
V RTSI_AI_START 26
V RTSI_G2_OUT 27
V RTSI_G2_GATE 28
V RTSI_G2_SRC 29
V RTSI_G2_Z 30
V RTSI_G3_OUT 31
V RTSI_G3_GATE 32
V RTSI_G3_SRC 33
V RTSI_G3_Z 34
V RTSI_DI_Convert 35
V RTSI_DI_Start1 36
V RTSI_DI_Start2 37
V RTSI_DI_Gate 38
V RTSI_DO_Update 39
V RTSI_DO_Start1 40
V RTSI_DO_Gate 41
V RTSI_PFI6 42
V RTSI_PFI7 43
V RTSI_PFI8 44
V RTSI_PFI9 45
V RTSI_PFI10 46
V RTSI_PFI11 47
V RTSI_PFI12 48
V RTSI_PFI13 49
V RTSI_PFI14 50
V RTSI_PFI15 51
V RTSI_PXIe_DStarA 52
V RTSI_PXIe_DStarB 53
V RTSI_G0_SampleClk 54
V RTSI_G1_SampleClk 55
V RTSI_G2_SampleClk 56
V RTSI_G3_SampleClk 57
V RTSI_IntTriggerA0 72
V RTSI_IntTriggerA1 73
V RTSI_IntTriggerA2 74
V RTSI_IntTriggerA3 75
V RTSI_IntTriggerA4 76
V RTSI_IntTriggerA5 77
V RTSI_IntTriggerA6 78
V RTSI_IntTriggerA7 79
#-------------------------------------------------------------------------------
# Enumerated type Trig_RTSI_i_Pin_Dir_t
#-------------------------------------------------------------------------------
E Trig_RTSI_i_Pin_Dir_t
V RTSI_Input 0
V RTSI_Output 1
#-------------------------------------------------------------------------------
# Enumerated type Trig_StarTrig_Output_Select_t
#-------------------------------------------------------------------------------
E Trig_StarTrig_Output_Select_t
V Star_IntTriggerA0 8
V Star_IntTriggerA1 9
V Star_IntTriggerA2 10
V Star_IntTriggerA3 11
V Star_IntTriggerA4 12
V Star_IntTriggerA5 13
V Star_IntTriggerA6 14
V Star_IntTriggerA7 15
#-------------------------------------------------------------------------------
# Enumerated type Trig_TB3_Select_t
#-------------------------------------------------------------------------------
E Trig_TB3_Select_t
V TB3_From_OSC 0
V TB3_From_PLL 1
#===============================================================================
# Register Group Triggers_and_Timing
#===============================================================================
#-------------------------------------------------------------------------------
# IntTriggerA_OutputSelectRegister_t Type Definition
T IntTriggerA_OutputSelectRegister_t 8 Writable --no-hardware-reset true
F IntTriggerA_i_Output_Select 7 . nTriggers::tTrig_IntTriggerA_i_Output_Select_t
@ IntTriggerA line output source selection
F Reserved 1
#-------------------------------------------------------------------------------
# PFI_OutputSelectRegister_t Type Definition
T PFI_OutputSelectRegister_t 8 Writable --no-hardware-reset true
F PFI_i_Output_Select 7 . nTriggers::tTrig_PFI_Output_Select_t
@ PFI line output source selection
F Reserved 1
#-------------------------------------------------------------------------------
# RTSI_OutputSelectRegister_t Type Definition
T RTSI_OutputSelectRegister_t 8 Writable --no-hardware-reset true
F RTSI_i_Output_Select 7 . nTriggers::tTrig_RTSI_i_Output_Select_t
@ RTSI line output source selection
F Reserved 1
#-------------------------------------------------------------------------------
# AnalogTrigControlRegister Register Definition
R AnalogTrigControlRegister 16 0xA0 Writable --no-hardware-reset true
F Analog_Trigger_Mode 3 . nTriggers::tTrig_Analog_Trigger_Mode_t
@ This bit selects the analog trigger mode of operation if the
@ analog trigger circuitry is enabled:
F Reserved 2
F Analog_Trigger_Reset 1 Strobe
@ This bit clears the hysteresis registers in the analog trigger
@ circuit. Set this bit to 1 at the time you arm a timing engine
@ with which you want to use the analog trigger circuit.
@ Before setting this bit to 1, make sure that the analog trigger
@ is not being used by any other timing engine in the STC3.
F Reserved 2
F Atrig_Sel 2 . nTriggers::tTrig_Atrig_Sel_t
@ This bitfield sets the value of the Atrig_Sel pins. This is used
@ to select between the output of the PGIA or the APFI pins.
F Reserved 6
#-------------------------------------------------------------------------------
# FOUT_Register Register Definition
R FOUT_Register 16 0xA2 Writable
F FOUT_Divider 4
@ This bit selects the divide ratio for the FOUT output signal.
@ If this bitfield is zero, then the division ratio will be 16:
@ FOUT = FOUT_TIMEBASE divided by 16. Otherwise, the division
@ ratio will be the value of this bitfield (1 to 15).
F Reserved 8
F FOUT_FastTB_DivideBy2 1 . nTriggers::tTrig_FOUT_FastTB_DivideBy2_t
@ This bit determines whether to divide the fast timebase used
@ in the FOUT pin.
F Reserved 1
F FOUT_Timebase_Select 1 . nTriggers::tTrig_FOUT_Timebase_Select_t
@ This bit selects the timebase used for FOUT, that is FOUT_TIMEBASE:
F FOUT_Enable 1 . nTriggers::tTrig_FOUT_Enable_t
@ Setting this bit to 1 enables and starts frequency output on
@ the FOUT signal, which can be routed to PFI pins: To change
@ the frequency divider value, first clear this bit, then change
@ FOUT_Divider, and set this bit again. If this bit is clear,
@ FOUT is disabled.
#-------------------------------------------------------------------------------
# PFI_Direction_Register Register Definition
R PFI_Direction_Register 16 0xA4 Writable --no-hardware-reset true
F PFI0_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI0.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI1_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI1.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI2_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI2.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI3_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI3.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI4_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI4.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI5_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI5.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI6_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI6.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI7_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI7.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI8_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI8.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI9_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI9.
@ NOTE: Writing to this register also initiates a
@ command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI10_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI10.
@ NOTE: Writing to this register also initiates
@ a command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI11_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI11.
@ NOTE: Writing to this register also initiates
@ a command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI12_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI12.
@ NOTE: Writing to this register also initiates
@ a command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI13_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI13.
@ NOTE: Writing to this register also initiates
@ a command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI14_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI14.
@ NOTE: Writing to this register also initiates
@ a command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
F PFI15_Pin_Dir 1 . nTriggers::tTrig_PFI_i_Pin_Dir_t
@ This bit selects the direction of the bidirectional pin PFI15.
@ NOTE: Writing to this register also initiates
@ a command transaction to the DAQ-6202, which sets the PFI pin
@ to the right direction. This transaction holds the bus until
@ complete.
#-------------------------------------------------------------------------------
# RTSI_Trig_Direction_Register Register Definition
R RTSI_Trig_Direction_Register 16 0xA6 Writable
F Reserved 8
F RTSI0_Pin_Dir 1 . nTriggers::tTrig_RTSI_i_Pin_Dir_t
@ This bit selects the output of the bidirectional pin RTSI0
F RTSI1_Pin_Dir 1 . nTriggers::tTrig_RTSI_i_Pin_Dir_t
@ This bit selects the output of the bidirectional pin RTSI1
F RTSI2_Pin_Dir 1 . nTriggers::tTrig_RTSI_i_Pin_Dir_t
@ This bit selects the output of the bidirectional pin RTSI2
F RTSI3_Pin_Dir 1 . nTriggers::tTrig_RTSI_i_Pin_Dir_t
@ This bit selects the output of the bidirectional pin RTSI3
F RTSI4_Pin_Dir 1 . nTriggers::tTrig_RTSI_i_Pin_Dir_t
@ This bit selects the output of the bidirectional pin RTSI4
F RTSI5_Pin_Dir 1 . nTriggers::tTrig_RTSI_i_Pin_Dir_t
@ This bit selects the output of the bidirectional pin RTSI5
F RTSI6_Pin_Dir 1 . nTriggers::tTrig_RTSI_i_Pin_Dir_t
@ This bit selects the output of the bidirectional pin RTSI6
F RTSI7_Pin_Dir 1 . nTriggers::tTrig_RTSI_i_Pin_Dir_t
@ This bit selects the output of the bidirectional pin RTSI7
#-------------------------------------------------------------------------------
# RTSI_OutputSelectRegister_i Register Definition
TRA RTSI_OutputSelectRegister_i%d RTSI_OutputSelectRegister_t 0xA8 8 RTSI_OutSel%d --step 1
#-------------------------------------------------------------------------------
# PFI_Filter_Register_0 Register Definition
R PFI_Filter_Register_0 16 0xb0 Writable
F PFI0_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 0 Filter Selection.
F Reserved 1
F PFI1_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 1 Filter Selection.
F Reserved 1
F PFI2_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 2 Filter Selection.
F Reserved 1
F PFI3_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 3 Filter Selection.
F Reserved 1
#-------------------------------------------------------------------------------
# PFI_Filter_Register_1 Register Definition
R PFI_Filter_Register_1 16 0xb2 Writable
F PFI4_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 4 Filter Selection.
F Reserved 1
F PFI5_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 5 Filter Selection.
F Reserved 1
F PFI6_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 6 Filter Selection.
F Reserved 1
F PFI7_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 7 Filter Selection.
F Reserved 1
#-------------------------------------------------------------------------------
# PFI_Filter_Register_2 Register Definition
R PFI_Filter_Register_2 16 0xb4 Writable
F PFI8_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 8 Filter Selection.
F Reserved 1
F PFI9_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 9 Filter Selection.
F Reserved 1
F PFI10_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 10 Filter Selection.
F Reserved 1
F PFI11_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 11 Filter Selection.
F Reserved 1
#-------------------------------------------------------------------------------
# PFI_Filter_Register_3 Register Definition
R PFI_Filter_Register_3 16 0xb6 Writable
F PFI12_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 12 Filter Selection.
F Reserved 1
F PFI13_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 13 Filter Selection.
F Reserved 1
F PFI14_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 14 Filter Selection.
F Reserved 1
F PFI15_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ PFI line 15 Filter Selection.
F Reserved 1
#-------------------------------------------------------------------------------
# STAR_Trig_Register Register Definition
R STAR_Trig_Register 16 0xB8 Writable
F Star_Trig_Output_Select 4 . nTriggers::tTrig_StarTrig_Output_Select_t
@ This bit selects the signal routed to the Star_Trig Pin when
@ used as an output.
F Reserved 11
F Star_Trig_Pin_Dir 1
@ This bit selects the direction of the Star_Trig pin
#-------------------------------------------------------------------------------
# PFI_OutputSelectRegister_i Register Definition
TRA PFI_OutputSelectRegister_i%d PFI_OutputSelectRegister_t 0xBA 16 PFI_OutSel%d --step 1
#-------------------------------------------------------------------------------
# DStarC_Trig_Register Register Definition
R DStarC_Trig_Register 16 0xCA Writable
F DStarC_Output_Select 4 . nTriggers::tTrig_StarTrig_Output_Select_t
@ This bit selects the signal routed to the DStarC Pin when enabled.
F Reserved 8
F Reserved 2
F Reserved 1
F DStarC_Enable 1
@ This bit enables DStarC to drive signals out to the system
#-------------------------------------------------------------------------------
# Clock_And_Fout2_Register Register Definition
R Clock_And_Fout2_Register 16 0xDA Writable
F PLL_In_Source_Select 5 . nTriggers::tTrig_PLL_In_Source_Select_t
@ These bits select the Reference Clock In for the PLL on the STC
@ 3 ASIC.
F Reserved 1
F TB3_Select 1 . nTriggers::tTrig_TB3_Select_t
@ This bit controls the Mux that selects between the two possible
@ sources for the internal clock TB3.
F Reserved 9
#-------------------------------------------------------------------------------
# PLL_Control_Register Register Definition
R PLL_Control_Register 32 0xDC Writable --initial-value 0x6000
F Reserved 8
F PLL_OutputDivider 6
@ PLL Output Divider (Binary value+1, so 0 => div by 1). These bits
@ set the division ratio for the output of the VCO.
F PLL_Multiplier 7
@ PLL Multiplier or Feedback Divider Value (Binary value+1, so
@ 0 => div by 1). These bits set the division ratio for the feedback
@ path of the PLL.
F PLL_RefDivisor 7
@ Reference Divider Value (Binary value + 1, so 0 => div by 1).
@ These bits set the division ratio applied to the Reference
@ Clock.
F PLL_Filter_Range 3 . nTriggers::tTrig_PLL_Filter_Range_t
@ These bits set the PLL loop filter to work wirh the post-reference
@ divider frequency. Choose the highest valid range for
@ best jitter performance.
F PLL_Enable 1
@ When this bit is set, it enables the PLL to start locking to
@ the Reference Clock In signal. When this bit is cleared, the
@ PLL is disabled, and the output of the PLL is forced to zero.
#-------------------------------------------------------------------------------
# PLL_Status_Register Register Definition
R PLL_Status_Register 16 0xDC Readable
F PLL_TimerExpired 1 . nTriggers::tTrigPllLockedStatus_t
@ This bit shows the status of the PLL Lock timer. Any time any
@ of the parameters of the PLL (PLL_Divisor, PLL_Multiplier Reference
@ Clock In Source, or PLL_Enable) changes, a timer starts
@ counting and this bit is cleared. The counter counts for
@ 1.1 mS, which is considerable more than the lock time for
@ the PLL, and when the timer expires, this bit sets. This bit
@ does not check the actual locked status of the PLL. This bit
@ can be used with the HW_Pll_Locked to infer a problem with
@ the connections or operation of the the PLL. When this bit
@ asserts, but the HW_Pll_Locked is still zero, it means the PLL
@ has not locked within the expected period of time.
F HW_Pll_Locked 1 . nTriggers::tTrigPllLockedStatus_t
@ This bit shows the status of the PLL Lock indicator. This Signal
@ indicates a Lock has occurred in the PLL. The Lock bit will
@ go high when the phase margin between the input clock and
@ the feedback clock is within 0-5% of the input period. This
@ is the main lock indication for the PLL in the STC 3 ASIC.
F Reserved 14
#-------------------------------------------------------------------------------
# PFI_DI_Register Register Definition
R PFI_DI_Register 16 0xE0 Readable
F PFI_0_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 0 when it
@ is configured as an input.
F PFI_1_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 1 when it
@ is configured as an input.
F PFI_2_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 2 when it
@ is configured as an input.
F PFI_3_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 3 when it
@ is configured as an input.
F PFI_4_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 4 when it
@ is configured as an input.
F PFI_5_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 5 when it
@ is configured as an input.
F PFI_6_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 6 when it
@ is configured as an input.
F PFI_7_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 7 when it
@ is configured as an input.
F PFI_8_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 8 when it
@ is configured as an input.
F PFI_9_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 9 when it
@ is configured as an input.
F PFI_10_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 10 when it
@ is configured as an input.
F PFI_11_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 11 when it
@ is configured as an input.
F PFI_12_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 12 when it
@ is configured as an input.
F PFI_13_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 13 when it
@ is configured as an input.
F PFI_14_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 14 when it
@ is configured as an input.
F PFI_15_DI_Bitfield 1
@ This bitfield will represent the status of PFI pin 15 when it
@ is configured as an input.
#-------------------------------------------------------------------------------
# PFI_DO_Register Register Definition
R PFI_DO_Register 16 0xE0 Writable --no-hardware-reset true
F PFI_DO_Bf 16
@ These bitfields represent the value that will be output on the
@ PFI pins when they are configured to output the PFI_DO mode.
#-------------------------------------------------------------------------------
# PFI_WDT_SafeStateRegister Register Definition
R PFI_WDT_SafeStateRegister 16 0xE2 Writable
F PFI_WDT_SafeStateValue 16 Decoded
@ This is the safe value that the PFI lines will go to if the Watchdog
@ Timer is enabled, and the PFI lines have the safe state
@ enabled (through the PFI_WDT_ModeSelect_Register).
#-------------------------------------------------------------------------------
# PFI_WDT_ModeSelect_Register Register Definition
R PFI_WDT_ModeSelect_Register 32 0xE4 Writable
F PFI_WDT_ModeD0 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD1 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD2 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD3 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD4 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD5 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD6 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD7 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD8 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD9 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD10 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD11 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD12 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD13 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD14 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
F PFI_WDT_ModeD15 2 . nTriggers::tPFI_WDT_Mode_t
@ This bitfield determines what action will be taken by the corresponding
@ DO line in the event of a Watchdog Timer event.
#-------------------------------------------------------------------------------
# IntTriggerA_OutputSelectRegister_i Register Definition
TRA IntTriggerA_OutputSelectRegister_i%d IntTriggerA_OutputSelectRegister_t 0xE8 8 IntTriggerA_OutSel%d --step 1
#-------------------------------------------------------------------------------
# IntTrigA_Filter_Register_Lo Register Definition
R IntTrigA_Filter_Register_Lo 16 0xf8 Writable
F ITA0_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ Internal Trigger A line 0 Filter Selection.
F Reserved 1
F ITA1_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ Internal Trigger A line 1 Filter Selection.
F Reserved 1
F ITA2_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ Internal Trigger A line 2 Filter Selection.
F Reserved 1
F ITA3_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ Internal Trigger A line 3 Filter Selection.
F Reserved 1
#-------------------------------------------------------------------------------
# IntTrigA_Filter_Register_Hi Register Definition
R IntTrigA_Filter_Register_Hi 16 0xfa Writable
F ITA4_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ Internal Trigger A line 4 Filter Selection.
F Reserved 1
F ITA5_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ Internal Trigger A line 5 Filter Selection.
F Reserved 1
F ITA6_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ Internal Trigger A line 6 Filter Selection.
F Reserved 1
F ITA7_Filter_Select 3 . nTriggers::tTrig_Filter_Select_t
@ Internal Trigger A line 7 Filter Selection.
F Reserved 1
#-------------------------------------------------------------------------------
# Trig_Filter_Settings1_Register Register Definition
R Trig_Filter_Settings1_Register 16 0x100 Writable
F Trig_Filter_Custom_Period_1 9
@ If 'Custom_Filter_1' is selected as filter for a determined trigger
@ line, this timebase is used for the dedicated counter
@ of the line that waits for the signal to be stable a custom
@ period of time before a transition or a pulse is detected
F Reserved 1
F Trig_Filter_Custom_Timebase_1 2 . nTriggers::tTrig_Filter_Custom_Timebase_t
@ If 'Custom_Filter_1' is selected as filter for a determined trigger
@ line, this timebase is used for the dedicated counter
@ of the line that waits for the signal to be stable a custom
@ period of time before a transition or a pulse is detected
F Reserved 1
F Trig_Filter_Ext_Signal_Select 3 . nTriggers::tTrig_Filter_Ext_Signal_Select_t
@ If 'External_Signal' is selected as filter for a determined trigger
@ line, that line must be stable for two assertions of
@ this signal for a transition or pulse to be detected.
#-------------------------------------------------------------------------------
# Trig_Filter_Settings2_Register Register Definition
R Trig_Filter_Settings2_Register 16 0x102 Writable
F Trig_Filter_Custom_Period_2 9
@ If 'Custom_Filter_2' is selected as filter for a determined trigger
@ line, that line must be stable for this number of clock
@ periods of the selected timebase for a transition or pulse
@ to be detected
F Reserved 1
F Trig_Filter_Custom_Timebase_2 2 . nTriggers::tTrig_Filter_Custom_Timebase_t
@ If 'Custom_Filter_2' is selected as filter for a determined trigger
@ line, this timebase is used for the dedicated counter
@ of the line that waits for the signal to be stable a custom
@ period of time before a transition or a pulse is detected
F Reserved 4
#
#-------------------------------------------------------------------------------
# PLL_LockCount_Register Register Definition
R PLL_LockCount_Register 16 0x104 Writable --initial-value 0xD6D8
F PLL_LockCount 16
@ This bitfield determines the delay that the PLL_TimerExpired
@ status bit will wait before expiring after the PLL has been
@ enabled. The idea is to provide a minimum time as a lock
@ period before the PLL is used. Or, a reference time to know
@ when is the PLL Locked bit not going to assert any more because
@ the max locked period has been exceeded. The PLL minimum
@ lock time is spec'd at 50us @ 10MHz. The default value for
@ this register is 12500. This counter runs on BusClk. So this
@ value will translate to: 100us when BusClock is
@ 125MHz 325us when BusClock is 40.0 MHz
@ 400us when BusClock is 31.25MHz 650us when BusClock
@ is 20.0 MHz This is only the default value. This
@ register can be updated by SW.
#
#-------------------------------------------------------------------------------
# Sync100_Repeat_Count_Register Register Definition
R Sync100_Repeat_Count_Register 8 0x106 Writable --initial-value 0x08
F Sync100_Repeat_Count 8
@ This bit sets the delay value for the Sync100 repeater circuit.
@ The value written should be the value desired -2. (so the default
@ value of 8 means the delay is 10 cycles).