#****************************************************************************** # StreamCircuitRegMap.rbm # # (c) Copyright 2011 # National Instruments Corporation. # All rights reserved. # License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT # Refer to "MHDDK License Agreement.pdf" in the root of this distribution. # # Description: # rbm file for StreamCircuitRegMap. # This file is autogenerated. Do not modify it directly. # # All lines starting with # or C are comments # All lines starting with T define a register Type # All lines starting with TR define register name, type, offset # All lines starting with F are Fields within the preceding register, # Its name, size, attribute (Strobe|.) and type are defined. # #****************************************************************************** # Declaring RBM as a containable chip object. # This means all instances must specify an offset for it. --containable --generate-include "tStreamCircuitRegMapValues.h" #=============================================================================== # Register Group StreamCircuit #=============================================================================== #------------------------------------------------------------------------------- # DMAChannel Type Definition T DMAChannel 32 Readable|Writable F Reserved 12 F DMAChannelNumber 10 @ This field provides the DMA Channel Number to use. F Reserved 6 F Reserved 4 #------------------------------------------------------------------------------- # StreamControlStatusReg Register Definition R StreamControlStatusReg 32 0x800 Readable|Writable --no-soft-copy true F CISTCR_Enable 1 Strobe @ Writing a 1 to this bit enables the StreamTransferCountReg (CISTCR). @ This bit will return a 1 when the CISTCR is enabled @ and a 0 when it is disabled. The CISTCR is disabled at reset. @ When the CISTCR is enabled, data transfers are limited by @ the count. When the CISTCR is disabled, the circuit ignores @ its value and data transfers will be initiated indefinitely. @ Disabling CISTCR could be useful for finite transfers of an @ unknown size or when pre-triggering in host memory. However, @ when the CISTCR is disabled, packet network congestion can @ result. F CISTCR_Disable 1 Strobe @ Writing a 1 to this bit disables the StreamTransferCountReg (CISTCR). @ This bit will return a 0 when the CISTCR is enabled @ and a 1 when it is disabled. F CISTCR_Clear 1 Strobe @ Writing a 1 to this bit clears the StreamTransferCountReg (CISTCR). @ Generally this should be done when initializing a new @ operation. This bit is the only way to get the CISTCR into @ a known state since there is no way to write it directly. The @ count value can only be written additively. F CISATCR_AccessIgnored 1 @ This read only bit indicates when a write to the StreamAdditiveTransferCountReg @ (CISATCR) has been ignored. Writes to CISATCR @ result in 32-bit signed additions. If the result of an @ access is negative, the register is not affected by the write @ and this status bit sets. This bit updates on each write to @ CISATCR so it always reflects the last access. F Reserved 4 F DataTransferEnable 1 Strobe @ Writing a 1 to this bit enables the Stream Circuit to initiate @ data transfers. This bit will return a 1 when data transfers are enabled @ and a 0 when they are disabled. This bit clears on reset and when either @ of the StreamCircuitReset or StreamCircuitResetNotify bits is written @ with a 1. For input streams, writes will not be initiated @ before this bit is written with a 1. For output streams, writing @ a 1 to this bit will cause the Stream Circuit to begin @ sending out request packets. When data transfers @ are not enabled, both input and output streams may still service @ requests as long as the Stream Circuit is not in the process @ of being reset. F StreamCircuitReset 1 Strobe @ When this bit is written with a 1, the entire stream circuit @ will be synchronously reset. This can be used to initialize @ the Stream Circuit to a known state. The FIFO and application @ logic will not be reset. This bit clears itself. F StreamCircuitResetComplete 1 @ This read only bit indicates when a stream reset operation is @ complete. After either of the StreamCircuitReset or StreamCircuitResetNotify @ bits is written with a 1, this status bit @ will not set until all the following conditions are true: This bit sets on @ reset to indicate that the Stream Circuit is reset. This bit @ clears whenever the DataTransferEnable bit is written with @ a 1. F StreamCircuitResetNotify 1 Strobe @ Writing a 1 to this bit performs the same function as the StreamCircuitReset @ bit. The difference is this bit will generate @ a stream Done event after the Stream Circuit is reset. This @ allows software to be notified when @ the entire reset process is complete. Use of this bit with @ a CHInCh DMA channel requires the associated DMA channel @ in the CHInCh to be in the started state so that the done event @ can be processed. This bit clears itself. F Reserved 1 F DoneFlagSet 1 Strobe @ This bit is only implemented for output Stream Circuits. Writing @ a 1 to this bit sets the Done flag, which indicates that @ no more data should be received. The Done flag will also be @ set when a stream packet is received with the Done bit set. @ The Done flag allows software to know when it is safe to reset @ the Stream Circuit. This bit will return a 1 when the Done @ flag is set and a 0 when it is clear. The Done Flag is cleared @ on reset and when either of the StreamCircuitReset or @ StreamCircuitResetNotify bits is written with a 1. This bit @ is only implemented for Output Stream Circuits. F InvalidPacketFlag 1 @ This read-only bit will return a 1 when a packet received by @ the Stream Circuit was invalid. This happens when an incoming @ packet references the wrong byte lane or transfers too much @ data for the resources available in the FIFO. For Input Stream @ Circuits, an incoming Split Read Request will have a Read @ Response returned with a Completion Status of Failure, plus @ no payload. For Output Stream Circuits, an incoming Posted @ Write Request or Read Response will be received but ignored. @ This bit clears on reset or when any of the StreamCircuitReset, @ StreamCircuitResetNotify, or RejectedPacketClear bits @ is written with a 1. F InvalidPacketClear 1 Strobe @ Writing a 1 to this bit clears the InvalidPacketFlag. F Reserved 1 F Reserved 1 F FifoEmpty 1 @ This read-only register returns a 1 when the FIFO is empty. F Reserved 13 #------------------------------------------------------------------------------- # StreamAdditiveTransferCountReg Register Definition R StreamAdditiveTransferCountReg 32 0x810 Writable --no-soft-copy true F StreamAdditiveTransferCount 32 @ The value written to this field is added to the current value @ of the Stream Transfer Count Register (CISTCR). This field @ is interpreted as a 32-bit signed value. The units are bytes. @ Results of writing to this register are accurate regardless @ of the timing of the write relative to the processing of data @ in the stream. So the Endpoint Interface handles the case @ that the write occurs at the same time that hardware is decreasing @ CISTCR due to the issuing of a new stream request. @ Software is responsible for ensuring that any writes to this @ field do not cause the CISTCR to overflow. In most applications @ software maintains status about DMA progress. This same @ status could be used for ensuring that writes to this register @ don't overflow CISTCR. This field should always be written @ with a 32-bit access. #------------------------------------------------------------------------------- # StreamTransferCountReg Register Definition R StreamTransferCountReg 32 0x810 Readable --no-soft-copy true F StreamTransferCount 32 @ This register limits the number of bytes that will be transferred @ with the Stream Circuit. As the Endpoint Interface initiates @ transfers in Stream space, the value in this register @ is decreased by the amount of data requested. The device will @ never request more bytes than the amount indicated by the @ current value of the register. Once the register reaches 0 the @ data stream is paused. The Endpoint Interface is designed @ to transfer data until this register reaches 0. It will not @ pause a few bytes sooner due to data alignment or any other @ simplification. This is intended for DMA progress control. @ The Endpoint Interface is designed to allow writes to this field @ to occur while the data stream is active. When reading @ this field the value returned is not guaranteed to be coherent @ with DMA data transfers in host memory. This register resets @ to an unknown value and should be initialized with the CISTCR_Clear @ bit prior to or in the same access in which the @ DataTransferEnable bit is set. #------------------------------------------------------------------------------- # StreamFifoSizeReg Register Definition R StreamFifoSizeReg 32 0x814 Readable F StreamFifoSize 32 @ This is the size of the Stream Circuit's data FIFO in bytes. @ It is an actual size in bytes, though the last few bytes may @ not be usable by a stream circuit depending on the sample width. @ To find the number of samples that the FIFO can store, @ divide this value by the number of bytes per sample and round @ down. #------------------------------------------------------------------------------- # StreamTransferLimitReg Register Definition R StreamTransferLimitReg 32 0x81C Readable|Writable --no-hardware-reset true F StreamMinPayloadSize 16 @ The value of this field is the smallest payload size that can @ be used by the Stream Circuit when sending out request packets. @ The exception to this is when the StreamTransferCountReg @ (CISTCR) is below this value or eviction occurs. When this @ happens, the remainder of the available data is transferred. @ To ensure that data transfers occur, program this value with @ a value less than or equal to the StreamMaxPayloadSize value @ so that requests will actually happen. This field defaults @ to the maximum on power-up (for high throughput). F StreamMaxPayloadSize 16 @ The value of this field is the largest payload size that can @ be used by the Stream Circuit when sending out request packets. @ This field defaults to the maximum on power-up. #------------------------------------------------------------------------------- # StreamEvictionReg Register Definition R StreamEvictionReg 32 0x820 Readable|Writable --no-hardware-reset true F EvictionTime 10 @ The value to preload into the eviction timer. This defaults to @ 0x20, or about one microsecond for a 31.25 MHz bus clock. F Reserved 21 F DisableEviction 1 @ When set, the eviction timer is disabled, and StreamMinPayloadSize @ will always be considered. When cleared, the eviction @ timer will trigger data communications even when less than StreamMinPayloadSize @ bytes can be transferred. #------------------------------------------------------------------------------- # StreamTransactionLimitReg Register Definition R StreamTransactionLimitReg 32 0x824 Readable|Writable --no-hardware-reset true F TransactionLimit 8 @ This field controls the number of transactions the Output Stream @ Circuit is capable of simultaneously generating. Valid values @ for this field range from 1 to MaxTransactionLimit. Do @ not write to this field while data transfers are enabled with @ DataTransferEnable. F MaxTransactionLimit 8 @ This read only field tells how many transactions the Output Stream @ Circuit is capable of simultaneously generating. F Reserved 16 #------------------------------------------------------------------------------- # DMAChannel Register Definition TRA DMAChannel%d DMAChannel 0x904 1 DMAChannel%d --step 16