#****************************************************************************** # OutTimer.rbm # # (c) Copyright 2011 # National Instruments Corporation. # All rights reserved. # License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT # Refer to "MHDDK License Agreement.pdf" in the root of this distribution. # # Description: # rbm file for OutTimer. # This file is autogenerated. Do not modify it directly. # # All lines starting with # or C are comments # All lines starting with T define a register Type # All lines starting with TR define register name, type, offset # All lines starting with F are Fields within the preceding register, # Its name, size, attribute (Strobe|.) and type are defined. # #****************************************************************************** # Declaring OutTimer RBM as a containable chip object. # This means all instances must specify an offset for it. --containable --generate-include "tOutTimerValues.h" #=============================================================================== # Register Group Enumerated_Types #=============================================================================== #------------------------------------------------------------------------------- # Enumerated type OutTimerSyncMode_t #------------------------------------------------------------------------------- E OutTimerSyncMode_t V SyncDefault 0 V SyncSlave 1 V SyncMaster 2 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Armed_t #------------------------------------------------------------------------------- E OutTimer_Armed_t V Disarmed 0 V Armed 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_BC_Gate_t #------------------------------------------------------------------------------- E OutTimer_BC_Gate_t V BC_Gate_Inactive 0 V BC_Gate_Active 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_BC_Q_t #------------------------------------------------------------------------------- E OutTimer_BC_Q_t V BC_St_WAIT 0 V BC_St_CNT 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_BC_Reload_Mode_t #------------------------------------------------------------------------------- E OutTimer_BC_Reload_Mode_t V BC_Reload_No_Change 0 V BC_Reload_Switch_On_BC_TC 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Continuous_t #------------------------------------------------------------------------------- E OutTimer_Continuous_t V FiniteOp 0 V ContinuousOp 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Disabled_Enabled_t #------------------------------------------------------------------------------- E OutTimer_Disabled_Enabled_t V Disabled 0 V Enabled 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Error_t #------------------------------------------------------------------------------- E OutTimer_Error_t V No_error 0 V Error 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_External_Gate_t #------------------------------------------------------------------------------- E OutTimer_External_Gate_t V ExtGate_Pause_Operation 0 V ExtGate_Enable_Operation 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_FIFO_Empty_t #------------------------------------------------------------------------------- E OutTimer_FIFO_Empty_t V Not_empty 0 V Empty 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_FIFO_Full_t #------------------------------------------------------------------------------- E OutTimer_FIFO_Full_t V Not_full 0 V Full 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_FIFO_Half_Full_t #------------------------------------------------------------------------------- E OutTimer_FIFO_Half_Full_t V Half_full_or_less 0 V More_than_half_full 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_FIFO_Mode_t #------------------------------------------------------------------------------- E OutTimer_FIFO_Mode_t V FifoMode_Empty 0 V FifoMode_Less_Than_Half_Full 1 V FifoMode_Less_Than_Full 2 V FifoMode_Less_Than_Half_Full_to_Full 3 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Load_Source_t #------------------------------------------------------------------------------- E OutTimer_Load_Source_t V Reg_A 0 V Reg_B 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Mute_t #------------------------------------------------------------------------------- E OutTimer_Mute_t V Normal_buffer 0 V Mute_buffer 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Polarity_t #------------------------------------------------------------------------------- E OutTimer_Polarity_t V Rising_Edge 0 V Falling_Edge 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Software_Gate_t #------------------------------------------------------------------------------- E OutTimer_Software_Gate_t V SwGate_Enable_operation 0 V SwGate_Pause_operation 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Start1_Export_Mode_t #------------------------------------------------------------------------------- E OutTimer_Start1_Export_Mode_t V ExportSynchronizedTriggers 0 V ExportEdgeDetectedTriggers 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Stop_On_Error_t #------------------------------------------------------------------------------- E OutTimer_Stop_On_Error_t V Continue_on_Error 0 V Stop_on_Error 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_TMRDACWRs_In_Progress_t #------------------------------------------------------------------------------- E OutTimer_TMRDACWRs_In_Progress_t V WritesCompleted 0 V WritesInProgress 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Trigger_t #------------------------------------------------------------------------------- E OutTimer_Trigger_t V Has_Not_Happened 0 V Has_Happened 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_UC_Q_t #------------------------------------------------------------------------------- E OutTimer_UC_Q_t V UC_Idle 0 V UC_Counting 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_UC_Reload_Mode_t #------------------------------------------------------------------------------- E OutTimer_UC_Reload_Mode_t V No_Change 0 V Switch_Every_UC_TC 1 V Switch_Every_BC_TC 2 V Alternate_First_Period_Every_BC_TC 3 #------------------------------------------------------------------------------- # Enumerated type OutTimer_UI_Count_Enabled_t #------------------------------------------------------------------------------- E OutTimer_UI_Count_Enabled_t V UI_CountNotEnabled 0 V UI_CoundIsEnabled 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_UI_Load_Switch_Pending_t #------------------------------------------------------------------------------- E OutTimer_UI_Load_Switch_Pending_t V No_Switch_Pending 0 V Switch_Pending 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_UI_Q_t #------------------------------------------------------------------------------- E OutTimer_UI_Q_t V UI_St_WAIT 0 V UI_St_CNT 1 #------------------------------------------------------------------------------- # Enumerated type OutTimer_UI_Reload_Mode_t #------------------------------------------------------------------------------- E OutTimer_UI_Reload_Mode_t V UI_Reload_No_Change 0 V UI_Reload_Switch_On_UC_TC_First 4 V UI_Reload_Switch_On_UC_TC 5 V UI_Reload_Switch_On_BC_TC_First 6 V UI_Reload_Switch_On_BC_TC 7 #------------------------------------------------------------------------------- # Enumerated type OutTimer_UI_Source_Select_t #------------------------------------------------------------------------------- E OutTimer_UI_Source_Select_t V UI_Src_TB3 0 V UI_Src_PFI0 1 V UI_Src_PFI1 2 V UI_Src_PFI2 3 V UI_Src_PFI3 4 V UI_Src_PFI4 5 V UI_Src_PFI5 6 V UI_Src_PFI6 7 V UI_Src_PFI7 8 V UI_Src_PFI8 9 V UI_Src_PFI9 10 V UI_Src_RTSI0 11 V UI_Src_RTSI1 12 V UI_Src_RTSI2 13 V UI_Src_RTSI3 14 V UI_Src_RTSI4 15 V UI_Src_RTSI5 16 V UI_Src_RTSI6 17 V UI_Src_DStarA 18 V UI_Src_TB2 19 V UI_Src_Star_Trigger 20 V UI_Src_PFI10 21 V UI_Src_PFI11 22 V UI_Src_PFI12 23 V UI_Src_PFI13 24 V UI_Src_PFI14 25 V UI_Src_PFI15 26 V UI_Src_RTSI7 27 V UI_Src_TB1 28 V UI_Src_PXI_Clk10 29 V UI_Src_Analog_Trigger 30 V UI_Src_DStarB 31 #------------------------------------------------------------------------------- # Enumerated type OutTimer_Write_Switch_t #------------------------------------------------------------------------------- E OutTimer_Write_Switch_t V Write_A 0 V Write_Inactive_Register 1 #=============================================================================== # Register Group OutTimer #=============================================================================== #------------------------------------------------------------------------------- # Command_1_Register Register Definition R Command_1_Register 32 0x00 Writable --no-soft-copy true F START1_Pulse 1 Strobe @ Setting this bit to 1 sends a AO_START1 trigger to the AO_BC, @ AO_UC, and AO_UI counters if the AO_START1 software strobe @ is selected (AO_START1_Select is set to 0). This bit is cleared @ automatically. F Reserved 3 F BC_Switch_Load_On_TC 1 Strobe @ Setting this bit to 1 causes the AO_BC counter to switch load @ registers at the next BC_TC. This bit is cleared automatically. @ This bit has no effect if the BC_Reload_Mode is set to @ a value different than 'BC_Reload_No_Change' F UC_Switch_Load_On_TC 1 Strobe @ Setting this bit to 1 causes the AO_UC counter to switch load @ registers at the next UC_TC. This bit is cleared automatically. @ This bit has no effect if the UC_Reload_Mode is set to @ a value different than 'No_Change' F UC_Switch_Load_On_BC_TC 1 Strobe @ Setting this bit to 1 causes the AO_UC counter to switch load @ registers at the next BC_TC. This bit is cleared automatically. @ This bit has no effect if the UC_Reload_Mode is set to @ a value different than 'No_Change' F UI_Switch_Load_On_TC 1 Strobe @ Setting this bit to 1 causes the AO_UI counter to switch the @ load registers at the next UI_TC. You can use this bit to change @ the update rate during waveform generation at the next @ update event. This bit is cleared automatically. This bit has @ no effect if the UI_Reload_Mode is set to a value different @ than 'UI_Reload_No_Change' F UI_Switch_Load_On_UC_TC 1 Strobe @ Setting this bit to 1 causes the AO_UI counter to switch load @ registers on the next UC_TC. This bit is cleared automatically. @ You can use this bit to change the update rate during waveform @ generation at the end of the current buffer. This bit @ has no effect if the UI_Reload_Mode is set to a value different @ than 'UI_Reload_No_Change' F UI_Switch_Load_On_BC_TC 1 Strobe @ Setting this bit to 1 causes the AO_UI counter to switch load @ registers at the next BC_TC. You can use this bit to change @ the update rate during waveform generation at the end of the @ current MISB. This bit is cleared automatically. This bit @ has no effect if the UI_Reload_Mode is set to a value different @ than 'UI_Reload_No_Change' F Reserved 2 F UI_Cancel_Load_Switch 1 Strobe @ Setting this bit to 1 causes any switch pending in the load source @ for the UI counter to be cancelled. This only works if @ the switch pending was caused by another strobe bit in this @ register (see related bitfields). F Reserved 1 F End_On_UC_TC 1 Strobe @ Setting this bit to 1 causes the AO_BC, AO_UC, and AO_UI counters @ to be disarmed at the next UC_TC. You can set this bit @ to stop waveform generation in the continuous mode. This action @ is internally synchronized to the falling edge of the AO_UC @ source. This bit is cleared automatically. F End_On_BC_TC 1 Strobe @ Setting this bit to 1 causes the AO_BC, AO_UC, and AO_UI counters @ to be stopped, but not disarmed, at the next BC_TC. You @ can set this bit to stop waveform generation in the continuous @ mode so that the AO timing engine ends up in a retriggerable @ state. This action is internally synchronized to the falling @ edge of the AO_UC source. This bit is cleared automatically. F Update_Pulse 1 Strobe @ Setting this bit to 1 produces a pulse on the AO_UPDATE output @ signals if the signals are enabled for output and if AO_UPDATE @ pulses are not blocked. AO_UPDATE pulses can be blocked @ by the external gate or by AO_Software_Gate. The pulsewidth @ of the output signals is determined by AO_UPDATE_Pulse_Width. @ This bit is cleared automatically. The AO timing engine must @ be armed for this bit to work F Reserved 4 F BC_Load 1 Strobe @ If the AO_BC counter is disarmed, this bit loads the AO_BC counter @ with the contents of the selected AO_BC load register. @ If the AO_BC counter is armed, writing to this bit has no effect. @ This bit is cleared automatically. F BC_Arm 1 Strobe @ This bit arms the AO_BC counter. The counter remains armed, and @ the bit remains set, until it is disarmed either by hardware @ or by setting AO_Disarm to 1.

NOTE: All Arm @ bits used for a given acquisition should be set on the same @ register write F UC_Load 1 Strobe @ If the AO_UC counter is disarmed, this bit loads the AO_UC counter @ with the contents of the selected AO_UC load register @ (A or B). If the AO_UC counter is armed, writing to this bit @ has no effect. This bit is cleared automatically. F UC_Arm 1 Strobe @ This bit arms the AO_UC counter. The counter remains armed, and @ the bit remains set, until it is disarmed either by hardware @ or by setting AO_Disarm to 1.

NOTE: All Arm @ bits used for a given acquisition should be set on the same @ register write F UI_Load 1 Strobe @ If the AO_UI counter is disarmed, this bit loads the AO_UI counter @ with the contents of the selected AO_UI load register @ (A or B). If the AO_UI counter is armed, writing to this bit @ has no effect. This bit is cleared automatically. F UI_Arm 1 Strobe @ Setting this bit to 1 arms the AO_UI counter. The counter remains @ armed, and the bit remains set, until it is disarmed either @ by hardware or by setting AO_Disarm to 1.

NOTE: @ All Arm bits used for a given acquisition should be set @ on the same register write F Reserved 2 F Disarm 1 Strobe @ Setting this bit to 1 asynchronously disarms the AO_BC, AO_UC, @ and AO_UI counters. This bit is cleared automatically. F Reserved 2 #------------------------------------------------------------------------------- # Status_1_Register Register Definition R Status_1_Register 32 0x00 Readable F BC_Armed_St 1 . nOutTimer::tOutTimer_Armed_t @ This bit indicates whether the AO_BC counter is armed F BC_Next_Load_Source_St 1 @ This bit reflects the state of the load source for the BC counter F Write_Too_Fast_St 1 @ This bit indicates the detection of a Write_Too_Fast error, i.e. @ when a direct write is attempted before the previous @ write is updated by the timed update signal. F BC_Q_St 1 . nOutTimer::tOutTimer_BC_Q_t @ This field reflects the state of the AO_BC control circuit F BC_TC_Trigger_Error_St 1 . nOutTimer::tOutTimer_Error_t @ This bit indicates the detection of a BC_TC trigger error.
@ A BC_TC trigger error occurs when a AO_START1 trigger is @ received after the last BC_TC of a staged waveform but before @ AO_BC_TC_Interrupt_Ack is set to 1. This allows you to detect @ triggers which arrive before completion of the ISR. You @ can clear this bit by setting AO_BC_TC_Trigger_Error_Confirm @ to 1. F UI_Armed_St 1 . nOutTimer::tOutTimer_Armed_t @ This bit indicates whether the AO_UI counter is armed F UI_Next_Load_Source_St 1 @ Reflects the status of the next load of the UI counter F UI_Load_Switch_Pending_St 1 . nOutTimer::tOutTimer_UI_Load_Switch_Pending_t @ This bit indicates if there is any switch pending in the load @ source for the UI counter. This only reflects a switch pending @ if the switch is not automatic (the switch was requested @ using the bitfields in the command register). F UI_Count_Enabled_St 1 . nOutTimer::tOutTimer_UI_Count_Enabled_t @ If the AO_UI counter is armed, this bit indicates whether the @ AO_UI counter is enabled to count If the counter is disarmed, @ this bit should be ignored. F UI_Q_St 1 . nOutTimer::tOutTimer_UI_Q_t @ This field reflects the state of the AO_UI control circuit: F TMRDACWRs_In_Progress_St 1 . nOutTimer::tOutTimer_TMRDACWRs_In_Progress_t @ This bit indicates whether the TMRDACWR sequence initiated by @ an AO_UPDATE or by setting AO_Not_An_UPDATE to 1 has completed @

NOTE You can poll this bit if you want to wait @ for the DAC to load before arming the analog-output counters. @ The HW ensures that if this bit reads zero after writing @ AO_Not_An_UPDATE to 1, it means the HW is done writing to @ all DACs. F BC_Gate_St 1 . nOutTimer::tOutTimer_BC_Gate_t @ When the BC_GATE is enabled (see AO_BC_Gate_Enable), this bit @ indicates the state of the BC_GATE

NOTE The BC_GATE @ is active only when the AO_BC counter is enabled to count. @ When the BC_GATE is disabled, this bit is undefined. Disable @ the BC_GATE in the internal AO_UPDATE mode. F External_Gate_St 1 . nOutTimer::tOutTimer_External_Gate_t @ This bit indicates whether the external gate and software gate @ are set to enable waveform generation F UC_Q_St 1 . nOutTimer::tOutTimer_UC_Q_t @ This bit reflects state of the AO_UC control state machine. F UC_Armed_St 1 . nOutTimer::tOutTimer_Armed_t @ This bit indicates whether the AO_UC counter is armed F UC_Next_Load_Source_St 1 . nOutTimer::tOutTimer_Load_Source_t @ This bit indicates the next load source of the AO_UC counter F Reserved 1 F FIFO_Request_St 1 @ This bit indicates the status of the DMA request (output signal @ AOFREQ) and FIFO interrupt. AO_FIFO_Mode selects the condition @ on which to generate the FIFO interrupt. F Reserved 3 F UPDATE_St 1 . nOutTimer::tOutTimer_Trigger_t @ This bit indicates whether an AO_UPDATE has occurred.

NOTE @ You can clear this bit by setting AO_UPDATE_Interrupt_Ack @ to 1. F UC_TC_St 1 @ This bit indicates whether the AO_UC counter has reached TC. To @ clear this bit, set AO_UC_TC_Interrupt_Ack to 1. F BC_TC_St 1 @ This bit indicates whether the AO_BC counter has reached TC. @ This bit is set on the trailing edge of BC_TC. You can clear @ this bit by setting AO_BC_TC_Interrupt_Ack to 1. F START1_St 1 . nOutTimer::tOutTimer_Trigger_t @ This bit indicates that a valid AO_START1 trigger has been received @ by the STC3.

NOTE A valid AO_START1 trigger @ is one that is received while the AO_BC counter is armed and @ in the WAIT1 state. You can clear this bit by setting AO_START1_Interrupt_Ack @ to 1. F Overrun_St 1 . nOutTimer::tOutTimer_Error_t @ This bit indicates the detection of an overrun error.

NOTE @ An overrun error occurs when an AO_UPDATE command is @ issued to a DAC that was not loaded with data. This bit can @ be cleared by setting AO_Error_Interrupt_Ack to 1.

NOTE @ This bit may incorrectly indicate that an error occurred @ after the end of a waveform generation sequence if there @ is no more data in the buffer. You can avoid this false error @ by transferring one more point of data to the device than @ the waveform generation requires. F Underflow_St 1 . nOutTimer::tOutTimer_Error_t @ This bit indicates the detection of an underflow error. F BC_TC_Error_St 1 . nOutTimer::tOutTimer_Error_t @ This bit indicates the detection of a BC_TC error:

NOTE @ A BC_TC error occurs if AO_BC_TC_Interrupt_Ack is not @ set between two AO_BC TCs. This allows you to detect large interrupt @ latencies and potential problems associated with them. @ To clear this bit, set AO_BC_TC_Error_Confirm to 1. F FIFO_Empty_St 1 . nOutTimer::tOutTimer_FIFO_Empty_t @ This bit reflects the state of the AO empty flag from the data @ FIFO. F FIFO_Half_Full_St 1 . nOutTimer::tOutTimer_FIFO_Half_Full_t @ This bit reflects the state of the data FIFO Half Full flag

NOTE: @ The operation of this bit is similar to AI_FIFO_Half_Full @ in the InTimer section. For input operations, @ however, the FIFO requires service when it is MORE than half-full. @ For output operations, the FIFO requires service when it is @ HALF FULL OR LESS. For this reason, the input and @ output ISRs must check for opposite values when deciding @ on interrupt servicing. F FIFO_Full_St 1 . nOutTimer::tOutTimer_FIFO_Full_t @ This bit reflects the state of data FIFO Full flag. F Reserved 1 #------------------------------------------------------------------------------- # UI_Load_A_Register Register Definition R UI_Load_A_Register 32 0x04 Writable F UI_Load_A 32 @ This bitfield is the load value A for the AO_UI counter. If load @ register A is the selected AO_UI load register, the AO_UI @ counter loads the value contained in this bitfield on AO_UI_Load @ and on UI_TC.

CAUTION : To prevent register @ ready violations, this register should be written only once @ before the value is loaded via AO_UI_Load (in the Command @ register). #------------------------------------------------------------------------------- # UI_Save_Register Register Definition R UI_Save_Register 32 0x04 Readable F UI_Save 32 @ This bitfield reflects the contents of the AO_UI counter. Reading @ from this bitfield while the AO_UI counter is counting @ may result in an erroneous value. #------------------------------------------------------------------------------- # UI_Load_B_Register Register Definition R UI_Load_B_Register 32 0x08 Writable F UI_Load_B 32 @ This bitfield is the load value B for the AO_UI counter. If load @ register B is the selected AO_UI load register, the AO_UI @ counter loads the value contained in this bitfield on AO_UI_Load @ and on UI_TC.

CAUTION : To prevent register @ ready violations, this register should be written only once @ before the value is loaded via AO_UI_Load (in the Command @ register). #------------------------------------------------------------------------------- # UC_Load_A_Register Register Definition R UC_Load_A_Register 32 0x0C Writable F UC_Load_A 32 @ This bitfield is the load value A for the AO_UC counter. If load @ register A is the selected AO_UC load register, the AO_UC @ counter loads the value contained in this bitfield on AO_UC_Load @ and on UC_TC.

CAUTION : To prevent register @ ready violations, this register should be written only once @ before the value is loaded via AO_UC_Load (in the Command @ register). #------------------------------------------------------------------------------- # UC_Save_Register Register Definition R UC_Save_Register 32 0x0C Readable F UC_Save 32 @ This bitfield reflects the contents of the UC counter. It is @ always a safe read. When AO_Hold_BC_On_UC_Read is zero, the @ read reflects the current state of the UC counter with no side @ effects. When AO_Hold_BC_On_UC_Read is one, reading this @ field will always reflect the state of the UC counter but will @ also have the side effect of freezing the BC counter, allowing @ a true snapshot of the state of the counters. #------------------------------------------------------------------------------- # UC_Load_B_Register Register Definition R UC_Load_B_Register 32 0x10 Writable F UC_Load_B 32 @ This bitfield is the load value B for the AO_UC counter. If load @ register B is the selected AO_UC load register, the AO_UC @ counter loads the value contained in this bitfield on AO_UC_Load @ and on UC_TC.

CAUTION : To prevent register @ ready violations, this register should be written only once @ before the value is loaded via AO_UC_Load (in the Command @ register). #------------------------------------------------------------------------------- # BC_Load_A_Register Register Definition R BC_Load_A_Register 32 0x14 Writable F BC_Load_A 32 @ This bitfield is the load value A for the AO_BC counter. If load @ register A is the selected AO_BC load register, the AO_BC @ counter loads the value contained in this bitfield on AO_BC_Load @ and on BC_TC.

CAUTION: To prevent register @ ready violations, this register should be written only once @ before the value is loaded via AO_BC_Load (in the Command @ register). #------------------------------------------------------------------------------- # BC_Save_Register Register Definition R BC_Save_Register 32 0x14 Readable F BC_Save 32 @ This bitfield reflects the contents of the BC counter. It is @ always a safe read. When AO_Hold_BC_On_UC_Read is zero, the @ read reflects the current state of the BC counter. When AO_Hold_BC_On_UC_Read @ is one, the field will freeze after each AO_UC_Save @ read, allowing a true snapshot of the state of the @ counters. #------------------------------------------------------------------------------- # BC_Load_B_Register Register Definition R BC_Load_B_Register 32 0x18 Writable F BC_Load_B 32 @ This bitfield is the load value B for the AO_BC counter. If load @ register B is the selected AO_BC load register, the AO_BC @ counter loads the value contained in this bitfield on the @ AO_BC_Load and on BC_TC.

CAUTION: To prevent register @ ready violations, this register should be written only @ once before the value is loaded via AO_BC_Load (in the Command @ register). #------------------------------------------------------------------------------- # Mode_1_Register Register Definition R Mode_1_Register 32 0x1C Writable F BC_Write_Switch 1 . nOutTimer::tOutTimer_Write_Switch_t @ This bit enables the write switch feature of the AO_BC load registers. @ Writes to AO_BC load register A are directed to the @ next available load register for writing (either A or B). F BC_Reload_Mode 1 . nOutTimer::tOutTimer_BC_Reload_Mode_t @ This bit selects the reload mode for the AO_BC counter. You can @ use setting 1 in waveform staging to obtain a new buffer @ repetition count for each MISB. F BC_Initial_Load_Source 1 . nOutTimer::tOutTimer_Load_Source_t @ If the AO_BC counter is disarmed, this bit selects the initial @ AO_BC load register. If the AO_BC counter is armed, writing @ to this bit has no effect. F UI_Write_Switch 1 . nOutTimer::tOutTimer_Write_Switch_t @ This bit enables the write switch feature of the AO_UI load registers. @ Writes to AO_UI load register A are directed to the @ next available load register for writing (either A or B). F UI_Reload_Mode 3 . nOutTimer::tOutTimer_UI_Reload_Mode_t @ This bitfield selects the reload mode for the AO_UI counter F UI_Initial_Load_Source 1 . nOutTimer::tOutTimer_Load_Source_t @ If the AO_UI counter is disarmed, this bit selects the initial @ AO_UI load register. If the AO_UI counter is armed, writing @ to this bit has no effect. F Reserved 2 F UC_Write_Switch 1 . nOutTimer::tOutTimer_Write_Switch_t @ This bit enables the write switch feature of the AO_UC load registers. @ Writes to AO_UC load register A are directed to the @ next available load register for writing (either A or B). F UC_Initial_Load_Source 1 . nOutTimer::tOutTimer_Load_Source_t @ If the AO_UC counter is disarmed, this bit selects the initial @ AO_UC load register. If the AO_UC counter is armed, writing @ to this bit has no effect. F Reserved 1 F FIFO_Retransmit_Enable 1 . nOutTimer::tOutTimer_Disabled_Enabled_t @ This bit enables the local buffer mode.

In the local buffer @ mode, the contents of the data FIFO are regenerated when @ the FIFO empties. The AO timing engine accomplishes this by @ pulsing the AOFFRT signal when the FIFO empty condition is @ indicated the AOFEF. You can use the local buffer mode when @ the FIFO is large enough to hold the whole waveform to be generated @ and the waveform does not vary in time. F FIFO_Mode 2 . nOutTimer::tOutTimer_FIFO_Mode_t @ This bitfield selects the data FIFO condition on which to generate @ the FIFO interrupt. F Trigger_Once 1 @ Setting this bit to 1 causes the analog output timing sequence @ to stop on BC_TC. The AO_BC, AO_UC, and AO_UI counters are @ disarmed at this time. F Continuous 1 . nOutTimer::tOutTimer_Continuous_t @ This bit determines the behavior of the AO_BC, AO_UC, and AO_UI @ counters during BC_TC F Reserved 1 F UI_Source_Polarity 1 . nOutTimer::tOutTimer_Polarity_t @ This bit selects the active edge of the AO_UI source (the signal @ that is selected by AO_UI_Source_Select) F Reserved 2 F UI_Source_Select 5 . nOutTimer::tOutTimer_UI_Source_Select_t @ This bitfields selects the AO_UI source F UC_Reload_Mode 2 . nOutTimer::tOutTimer_UC_Reload_Mode_t @ This bit selects the reload mode for the AO_UC counter F Reserved 3 #------------------------------------------------------------------------------- # Mode_2_Register Register Definition R Mode_2_Register 32 0x20 Writable F Reserved 2 F Mute_A 1 . nOutTimer::tOutTimer_Mute_t @ This bit determines whether the programmed buffer is a mute buffer. @ Set this bit to 0 if you want AO_UPDATE and related signals @ to be generated while the AO_BC counter is using load @ register A as the active load register. Set this bit to 1 if @ you want the STC3 to suppress AO_UPDATE and related signals @ while the AO_BC counter is using load register A as the active @ load register. You can use the mute operation to obtain @ a pause between two real waveforms. You must set the AO_Mute_A @ bit to the correct value before the AO_BC counter begins @ using load register A. F Mute_B 1 . nOutTimer::tOutTimer_Mute_t @ This bit determines whether the programmed buffer is a mute buffer. @ Set this bit to 0 if you want AO_UPDATE and related signals @ to be generated while the AO_BC counter is using load @ register B as the active load register. Set this bit to 1 if @ you want the STC3 to suppress AO_UPDATE and related signals @ while the AO_BC counter is using load register B as the active @ load register. You can use the mute operation to obtain @ a pause between two real waveforms. You must set the AO_Mute_B @ bit to the correct value before the AO_BC counter begins @ using load register B. F Reserved 3 F SyncMode 2 . nOutTimer::tOutTimerSyncMode_t @ This bitfield determines the mode of operation of trigger synchronization. F Reserved 8 F Software_Gate 1 . nOutTimer::tOutTimer_Software_Gate_t @ This bit controls the software gate, which can be used to pause @ an analog output operation F Not_An_UPDATE 1 Strobe @ Setting this strobe bit causes the generation of an appropriate @ number of TMRDACWR pulses without generating any AO_UPDATE @ pulses. Use this bit during the AO configuration phase in @ the programming sequence to write the first point of the buffer @ into the DACs.

For the TMRDACWR pulses to be generated, @ AO_FIFO_Enable must be set to 1 and the data FIFO @ must contain data. F Stop_On_BC_TC_Error 1 . nOutTimer::tOutTimer_Stop_On_Error_t @ This bit determines whether output timing stops when a @ BC_TC error occurs. AO_BC_TC_Error_St is set in either case. F Stop_On_BC_TC_Trigger_Error 1 . nOutTimer::tOutTimer_Stop_On_Error_t @ This bit determines whether output timing stops when a @ BC_TC trigger error occurs.
AO_BC_TC_Trigger_Error_St @ is set in either case. F Stop_On_Overrun_Error 1 . nOutTimer::tOutTimer_Stop_On_Error_t @ This bit determines whether analog output timing will stop when @ an overrun error occurs. If this bit is set and an overrun @ error is detected, the AO_UPDATE pulses will be masked off @ until the overrun error is cleared by the AO_Error_Interrupt_Ack @ bit.
AO_Overrun_St is set in either case. F AOFREQ_Enable 1 . nOutTimer::tOutTimer_Disabled_Enabled_t @ This bit enables the FIFO Request signal. This bitfield has no @ effect, since the request condition is determined directly by @ the Stream Circuit. F Reserved 3 F Hold_BC_On_UC_Read 1 @ When this bit is '1', every time the UC counter is read, the @ value of the BC counter is held until it's read in order to @ keep correlation between counter readings. F Start1_Export_Mode 1 . nOutTimer::tOutTimer_Start1_Export_Mode_t @ This bit selects the signal appearing on the PFI pin when routed @ with the START1 signal for the correspondent instance of @ the Out timer F Reserved 1 F FIFO_Enable 1 . nOutTimer::tOutTimer_Disabled_Enabled_t @ This bit enables the TMRDACWR signal to generate pulses after @ each AO_UPDATE. This pulses generate FIFO reads as well as @ DacWr signals at the pins or the serial interfaces. F BC_Gate_Enable 1 . nOutTimer::tOutTimer_Disabled_Enabled_t @ This bit enables the BC_GATE. Enabling the BC_GATE allows external @ AO_UPDATE pulses to pass only when the AO_BC counter is @ enabled to count. Set this bit to 0 in the internal AO_UPDATE @ mode (AO_UPDATE_Source_Select is set to 0) or if you are @ using AO_UPDATE_Pulse. Otherwise, set to 1. F Reserved 1 #------------------------------------------------------------------------------- # Output_Control_Register Register Definition R Output_Control_Register 16 0x26 Writable --initial-value 0x1 F ExportedUpdatePolarity 1 . nOutTimer::tOutTimer_Polarity_t @ This bitfield determines the polarity of the update exported @ to PFI, RTSI and all other subsystems. If active high, the rising @ edge is the one that updates. If active low, the falling @ edge is the significant one. F Reserved 7 F Number_Of_Channels 8 @ This bitfield determines the number of analog output channels @ that are written. The channel order is defined by the configuration @ FIFO. #------------------------------------------------------------------------------- # Interrupt1_Register Register Definition R Interrupt1_Register 32 0x28 Writable --no-soft-copy true F BC_TC_Interrupt_Enable 1 Strobe @ This bit strobe enables the BC_TC interrupt. BC_TC interrupts @ are generated on the trailing edge of BC_TC. F START1_Interrupt_Enable 1 Strobe @ This bit strobe enables the AO_START1 interrupt. The AO_START1 @ interrupt is generated on valid AO_START1 triggers received @ by the STC3. A valid AO_START1 trigger is one that is received @ while the AO_BC counter is armed and in the WAIT1 state. F UPDATE_Interrupt_Enable 1 Strobe @ This bit strobe enables the AO_UPDATE interrupt. AO_UPDATE interrupts @ are generated on the trailing edge of AO_UPDATE. F Reserved 2 F Error_Interrupt_Enable 1 Strobe @ This bit strobe enables the Error interrupt. The Error interrupt @ is generated on the detection of an overrun error condition. F UC_TC_Interrupt_Enable 1 Strobe @ This bit strobe enables the UC_TC interrupt. UC_TC interrupts @ are generated on the leading edge of UC_TC. F Reserved 1 F FIFO_Interrupt_Enable 1 Strobe @ This bit strobe enables the FIFO interrupt. The FIFO interrupt @ is generated on the FIFO condition indicated by AO_FIFO_Mode. F Write_Too_Fast_Interrupt_Enable 1 Strobe @ This bit strobe enables the AO_Write_Too_Fast interrupt. The Error @ AO_Write_Too_Fast interrupt is generated when a direct write @ is attempted before the previous write is updated by the timed update signal. F Reserved 6 F Write_Too_Fast_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears the AO_Write_Too_Fast_St. This bit @ is cleared automatically. F Reserved 2 F BC_TC_Trigger_Error_Confirm 1 Strobe @ Setting this bit to 1 clears AO_BC_TC_Trigger_Error_St. This @ bit is cleared automatically. F BC_TC_Error_Confirm 1 Strobe @ Setting this bit to 1 clears AO_BC_TC_Error_St. This bit is cleared @ automatically. F Reserved 2 F UC_TC_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AO_UC_TC_St and acknowledges the @ UC_TC interrupt request if the UC_TC interrupt is enabled. @ This bit is cleared automatically. F BC_TC_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AO_BC_TC_St and acknowledges the @ BC_TC interrupt request if the BC_TC interrupt is enabled. @ This bit is cleared automatically. F START1_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AO_START1_St and acknowledges the @ AO_START1 interrupt request if the AO_START1 interrupt is @ enabled. This bit is cleared automatically. F UPDATE_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AO_UPDATE_St and acknowledges the @ AO_UPDATE interrupt request if the AO_UPDATE interrupt is @ enabled . This bit is cleared automatically. F Reserved 2 F Error_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AO_Overrun_St and acknowledges the @ Error interrupt request if the Error interrupt is enabled. @ This bit is cleared automatically. F Reserved 2 #------------------------------------------------------------------------------- # Interrupt2_Register Register Definition R Interrupt2_Register 32 0x2C Writable --no-soft-copy true F BC_TC_Interrupt_Disable 1 Strobe @ This bit strobe disables the BC_TC interrupt. BC_TC interrupts @ are generated on the trailing edge of BC_TC. F START1_Interrupt_Disable 1 Strobe @ This bit strobe disables the AO_START1 interrupt. The AO_START1 @ interrupt is generated on valid AO_START1 triggers received @ by the STC3. A valid AO_START1 trigger is one that is received @ while the AO_BC counter is armed and in the WAIT1 state. F UPDATE_Interrupt_Disable 1 Strobe @ This bit strobe disables the AO_UPDATE interrupt. AO_UPDATE interrupts @ are generated on the trailing edge of AO_UPDATE. F Reserved 2 F Error_Interrupt_Disable 1 Strobe @ This bit strobe disables the Error interrupt. The Error interrupt @ is generated on the detection of an overrun error condition. F UC_TC_Interrupt_Disable 1 Strobe @ This bit strobe disables the UC_TC interrupt. UC_TC interrupts @ are generated on the leading edge of UC_TC. F Reserved 1 F FIFO_Interrupt_Disable 1 Strobe @ This bit strobe disables the FIFO interrupt. The FIFO interrupt @ is generated on the FIFO condition indicated by AO_FIFO_Mode. F Write_Too_Fast_Interrupt_Disable 1 Strobe @ This bit strobe disables the AO_Write_Too_Fast interrupt. The @ Error AO_Write_Too_Fast interrupt is generated when a direct @ write is attempted before the previous write is updated by @ the timed update signal. F Reserved 6 F Write_Too_Fast_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears the AO_Write_Too_Fast_St. This bit @ is cleared automatically. F Reserved 2 F BC_TC_Trigger_Error_Confirm2 1 Strobe @ Setting this bit to 1 clears AO_BC_TC_Trigger_Error_St. This @ bit is cleared automatically. F BC_TC_Error_Confirm2 1 Strobe @ Setting this bit to 1 clears AO_BC_TC_Error_St. This bit is cleared @ automatically. F Reserved 2 F UC_TC_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AO_UC_TC_St and acknowledges the @ UC_TC interrupt request if the UC_TC interrupt is enabled. @ This bit is cleared automatically. F BC_TC_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AO_BC_TC_St and acknowledges the @ BC_TC interrupt request if the BC_TC interrupt is enabled. @ This bit is cleared automatically. F START1_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AO_START1_St and acknowledges the @ AO_START1 interrupt request if the AO_START1 interrupt is @ enabled. This bit is cleared automatically. F UPDATE_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AO_UPDATE_St and acknowledges the @ AO_UPDATE interrupt request if the AO_UPDATE interrupt is @ enabled. This bit is cleared automatically. F Reserved 2 F Error_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AO_Overrun_St and acknowledges the @ Error interrupt request if the Error interrupt is enabled. @ This bit is cleared automatically. F Reserved 2 #------------------------------------------------------------------------------- # Reset_Register Register Definition R Reset_Register 16 0x34 Writable --no-soft-copy true F Reset 1 Strobe @ Setting this bit to 1 resets the OutTimer. Setting this @ bit to 1 also clears all the status bits and interrupts related @ to analog output except those associated with the @ data FIFO. This bit is cleared automatically.

CAUTION @ Using this bitfield to reset the timer will also activate @ the ConfigReset. A strobe write to the Configuration_End @ bitfield must be executed after reseting the timer with this @ bitfield. (In a separate register access). F Configuration_Start 1 Strobe @ This bit holds the analog output circuitry in reset to prevent @ glitches on the output pins during configuration. You should @ set this bit to 1 when beginning the configuration process @ of the analog output circuitry. By doing this, you ensure @ that no spurious glitches appear on the output pins and on the @ internal circuit components. If you do not set this bit to @ 1, the STC3 may behave erroneously. You can clear this bit @ by setting Configuration_End to 1. F Configuration_End 1 Strobe @ This bit clears Configuration_Start, which holds the analog @ output circuitry in reset to prevent glitches on the output @ pins during configuration. Set this bit to 1 at the end of @ the configuration process of the analog output circuitry. This @ bit is cleared automatically. F FIFO_Clear 1 Strobe @ Writing to this register pulses the DAC_FIFO_Clear signal. Following @ a write to this bitfield a read (or bus flush) must @ occur to ensure that the FIFO reset has completed before passing @ data into the FIFO. F Reserved 12