NOTE: All Arm @ bits used for a given acquisition should be set on the same @ register write
F DIV_Load 1 Strobe @ If the AI_DIV counter is disarmed, this bit loads the AI_DIV @ counter with the contents of the AI_DIV load register. If the @ AI_DIV counter is armed, writing to this bit has no effect. @ This bit is cleared automatically. F DIV_Arm 1 Strobe @ This bit arms the AI_DIV counter. The counter remains armed (and @ the bit remains set) until it is disarmed, either by hardware @ or by setting AI_Disarm to 1.NOTE: All Arm @ bits used for a given acquisition should be set on the same @ register write
F SI_Load 1 Strobe @ If the AI_SI counter is disarmed, this bit loads the AI_SI counter @ with the contents of the selected AI_SI load register @ (A or B). If the AI_SI counter is armed, writing to this bit @ has no effect. This bit is cleared automatically. F SI_Arm 1 Strobe @ Setting this bit to 1 arms the AI_SI counter. The counter remains @ armed (and the bit remains set) until it is disarmed, either @ by hardware or by setting AI_Disarm to 1.NOTE: @ All Arm bits used for a given acquisition should be set @ on the same register write
F SI2_Load 1 Strobe @ This bitfield is load register A for the AI_SI2 counter. If load @ register A is the selected AI_SI2 load register, the AI_SI2 @ counter loads the value contained in this bitfield on AI_SI2_Load @ and on SI2_TC. F SI2_Arm 1 Strobe @ Setting this bit to 1 arms the AI_SI2 counter. The counter remains @ armed and the bit remains set until it is disarmed, either @ by hardware or by setting AI_Disarm to 1.NOTE: @ All Arm bits used for a given acquisition should be set @ on the same register write
F Disarm 1 Strobe @ Setting this bit to 1 asynchronously disarms the AI_SC, AI_SI, @ AI_SI2, and AI_DIV counters. This bit is cleared automatically. F Reserved 2 F START1_Pulse 1 Strobe @ Setting this bit to 1 sends an AI_START1 trigger to the counters @ if the AI_START1 software strobe is selected. The AI_START1 @ software strobe is selected when AI_START1_Select is set @ to 0. This bit is cleared automatically. F START2_Pulse 1 Strobe @ Setting this bit to 1 sends a AI_START2 trigger to the AI_SC @ counter if the AI_START2 software strobe is selected. The AI_START2 @ software strobe is selected when AI_START2_Select is @ set to 0. This bit is cleared automatically. F START_Pulse 1 Strobe @ Setting this bit to 1 sends an AI_START trigger to the counters @ if the AI_START software strobe is selected. You select the @ software strobe by setting AI_START_Select to 18. This bit @ is cleared automatically. F Reserved 1 F SC_Switch_Load_On_TC 1 Strobe @ Setting this bit to 1 causes the AI_SC counter to switch load @ registers at the next SC_TC. You can use this bit for staged @ analog input. This bit is cleared automatically. This bit @ has no effect if the SC_Reload_Mode is set to a value different @ than 'SC_Reload_No_Change' F Reserved 2 F SI_Switch_Load_On_TC 1 Strobe @ Setting this bit to 1 causes the AI_SI counter to switch load @ registers at its next TC. This action is internally synchronized @ to the falling edge of the internal signal SI_CLK. You @ can use this bit for scan rate change during an acquisition. @ This bit is cleared automatically. This bit has no effect @ if the SI_Reload_Mode is set to a value different than 'No_Change' F SI_Switch_Load_On_STOP 1 Strobe @ Setting this bit to 1 causes the AI_SI counter to switch load @ registers upon receiving a AI_STOP trigger. This action is @ internally synchronized to the falling edge of the internal @ signal SI_CLK. This bit is cleared automatically. This bit has @ no effect if the SI_Reload_Mode is set to a value different @ than 'No_Change' F SI_Switch_Load_On_SC_TC 1 Strobe @ Setting this bit to 1 causes the AI_SI counter to switch load @ registers at the next SC_TC. This action is internally synchronized @ to the falling edge of the internal signal SI_CLK. @ You use this bit for scan rate change during an acquisition @ for staged analog input. This bit is cleared automatically. @ This bit has no effect if the SI_Reload_Mode is set to a value @ different than 'No_Change' F Reserved 3 F SC_PreWaitCountTC_ErrorAck 1 Strobe @ This bit clears the SC_PreWaitCountTC_Error status F End_On_End_Of_Scan 1 Strobe @ Setting this bit to 1 disarms the AI_SC, AI_SI, AI_SI2, and AI_DIV @ counters at the next AI_STOP. You can use this bit to @ stop the acquisition in continuous acquisition mode. This bit @ is cleared automatically.NOTE: If you set this @ bit as part of a single point AI acquisition on one channel @ in single-wire mode, you will actually acquire two points. @ You may discard the second point.
F End_On_SC_TC 1 Strobe @ Setting this bit to 1 disarms the AI_SC, AI_SI, AI_SI2, and AI_DIV @ counters at the next SC_TC. You can use this bit to stop @ the acquisition in continuous acquisition mode. This bit @ is cleared automatically. #------------------------------------------------------------------------------- # Status_1_Register Register Definition R Status_1_Register 32 0x00 Readable F Reserved 1 F FIFO_Request_St 1 . nInTimer::tInTimer_FIFO_Request_St_t @ This bit indicates the status of the DMA request (internal signal @ AIFREQ) and the FIFO interrupt. AI_FIFO_Mode selects the @ condition on which to generate the DMA request and FIFO interrupt. F Reserved 2 F STOP_St 1 @ This bit indicates that a valid AI_STOP signal has been received @ by the AI timing engine. A valid AI_STOP trigger is one @ that is received while the AI_SC counter is enabled to count @ after a valid AI_START. This bit is cleared by setting AI_STOP_Interrupt_Ack @ to 1. Refer to the Interrupt Conditions topic @ for more information. F START_St 1 @ This bit indicates that a valid AI_START trigger has been received @ by the AI timing engine A valid AI_START trigger is one @ that is received while the AI_SC counter is enabled to count. @ You can clear this bit by setting AI_START_Interrupt_Ack @ to 1. Refer to Interrupt Conditions section for more information. F SC_TC_St 1 @ This bit indicates whether the AI_SC counter has reached TC You @ can clear this bit by setting AI_SC_TC_Interrupt_Ack to 1. @ Refer to the Interrupt Conditions section for more information. F START1_St 1 @ This bit indicates that a valid AI_START1 trigger has been received @ by the STC3. A valid AI_START1 trigger is one that is @ received while the AI_SC counter is armed and in the Idle state. @ This bit can be cleared by setting AI_START1_Interrupt_Ack @ to 1. Refer to Interrupt Conditions section for more information. F START2_St 1 @ This bit indicates whether a valid AI_START2 trigger has been @ received by the AI_SC counter in the pretrigger acquisition @ mode. A valid AI_START2 signal is one that is received while @ the AI_SC counter is in the Waiting for AI_START2 state. You @ can clear this bit by setting AI_START2_Interrupt_Ack to 1. @ Refer to the Interrupt Conditions section for more information. F SC_TC_Error_St 1 . nInTimer::tInTimer_Error_t @ This bit indicates the detection of an SC_TC error. An SC_TC error @ is detected if AI_SC_TC_Interrupt_Ack is not set between @ two AI_SC TCs. This allows you to detect large interrupt latencies @ and potential problems associated with them. To clear @ this bit, set SC_TC_Error_Confirm to 1. F Overflow_St 1 . nInTimer::tInTimer_Error_t @ This bit indicates the detection of an ADC overflow error. The @ overflow error indicates that an attempt was made to write @ the ADC result to a full AI data FIFO; that is, the reading @ from the FIFO is too slow to match the writing to the FIFO. @ If the overflow error occurs, at least one point of data has @ been lost. This bit is cleared by setting AI_Overflow_Interrupt_Ack @ to 1. F Overrun_St 1 . nInTimer::tInTimer_Error_t @ This bit indicates the detection of an ADC overrun error: The @ overrun error indicates that the AI_CONVERT interval is not @ long enough to complete a conversion. This bit can be cleared @ by setting AI_Overrun_Interrupt_Ack to 1. F FIFO_Empty_St 1 . nInTimer::tInTimer_FIFO_Empty_St_t @ This bit reflects the state of the AI FIFO empty internal signal (after @ the polarity selection), which indicates the AI data FIFO @ status F FIFO_Half_Full_St 1 @ This bit reflects the state of the AI FIFO half full internal signal (after @ the polarity selection), which indicates the AI data FIFO @ status: F FIFO_Full_St 1 . nInTimer::tInTimer_FIFO_Full_St_t @ This bit reflects the state of the AI FIFO FULL internal signal (after @ the polarity selection), which indicates the AI data FIFO @ status F ScanOverrun_St 1 . nInTimer::tInTimer_Error_t @ This bit indicates the detection of a ScanOverrun error. A ScanOverrun @ error is detected if an AI sample clock pulse comes @ in the middle of a scan interval (time between the sample clock @ and the convert pulse of the last channel for that sample). F SC_Armed_St 1 . nInTimer::tInTimer_Disarmed_Armed_t @ This bit indicates whether the AI_SC counter is armed F SC_Next_Load_Source_St 1 . nInTimer::tInTimer_Load_A_Load_B_t @ This bit indicates the next load source of the AI_SC counter. F Reserved 1 F SI_Armed_St 1 . nInTimer::tInTimer_Disarmed_Armed_t @ This bit indicates whether the AI_SI counter is armed F SI_Next_Load_Source_St 1 . nInTimer::tInTimer_Load_A_Load_B_t @ This bit indicates the next load source of the AI_SI counter. F SI_Counting_St 1 @ If the AI_SI counter is armed, this bit indicates whether the @ AI_SI counter is enabled to count. If the AI_SI counter is @ disarmed, this bit should be ignored. F SI2_Armed_St 1 . nInTimer::tInTimer_Disarmed_Armed_t @ This bit indicates whether the AI_SI2 counter is armed F SI2_Next_Load_Source_St 1 . nInTimer::tInTimer_Load_A_Load_B_t @ This bit indicates the next load source of the AI_SI2 counter. F DIV_Armed_St 1 . nInTimer::tInTimer_Disarmed_Armed_t @ This bit indicates whether the AI_DIV counter is armed F SC_Gate_St 1 @ This bit indicates the status of the AI_SC gate if the AI_SC @ gate is enabled: F Start_Stop_Gate_St 1 @ This bit indicates the status of the start/stop gate, if start/stop @ gating is enabled: F SC_PreWaitCountTC_St 1 @ Indicates that the SC_TC counter rolled over while waiting for @ the START2 trigger. Clear this bit using the SC_PreWaitCountTC_Interrupt_Ack @ bit. F Scan_In_Progress_St 1 @ This bit indicates whether a scan is currently in progress. The @ bit is set when a valid AI_START is received and the bit @ is cleared when a valid AI_STOP is received. F External_Gate_St 1 @ This bit indicates whether the external gate and the software @ gate are set to enable analog input operation: F Last_Shiftin_St 1 @ This bit indicates that the data corresponding to the last convert @ after the last SC_TC has been written to the FIFO. It @ is cleared by setting AI_SC_TC_Interrupt_Ack to 1. F SC_PreWaitCountTC_ErrorSt 1 @ Indicates that the SC_TC rolled over at least TWICE without an @ acknowledge while waiting for the START2 trigger in a pretrigger @ acquisition. Clear this bit with the SC_PreWaitCountTC_ErrorAck #------------------------------------------------------------------------------- # Mode_1_Register Register Definition R Mode_1_Register 32 0x04 Writable --initial-value 0x0001 F ExportedConvertPolarity 1 . nInTimer::tInTimer_Polarity_t @ This bit determines the polarity of the Convert signal that gets @ exported to PFI or RTSI or to other resources on the STC3. @ Its default value is one, which means Active Low signals. F SC_Reload_Mode 1 . nInTimer::tInTimer_SC_Reload_Mode_t @ This bitfield selects the reload mode for the AI_SC counter. @ You can use 1 for pretriggered acquisition mode and for staged @ analog input. F SC_Initial_Load_Source 1 . nInTimer::tInTimer_Load_A_Load_B_t @ If the AI_SC counter is disarmed, this bit selects the initial @ AI_SC load register. If the AI_SC counter is armed, this bit @ has no effect. F Reserved 1 F SI_Reload_Mode 3 . nInTimer::tInTimer_SI_Reload_Mode_t @ This bit selects the reload mode for the AI_SI counter. F SI_Initial_Load_Source 1 . nInTimer::tInTimer_Load_A_Load_B_t @ If the AI_SI counter is disarmed, this bit selects the initial @ AI_SI load register. If the AI_SI counter is armed, writing @ to this bit has no effect. F SI2_Reload_Mode 1 . nInTimer::tInTimer_SI2_Reload_Mode_t @ This bit selects the reload mode for the AI_SI2 counter. Set @ this bit to 1 in the internal AI_CONVERT mode to make the time @ intervals between the AI_START trigger and the first AI_CONVERT @ different from the time interval between AI_CONVERTs. F SI2_Initial_Load_Source 1 . nInTimer::tInTimer_Load_A_Load_B_t @ This bit selects the initial AI_SI2 load register. Do not change @ this bit while the counter is counting. F Reserved 1 F Reserved 1 F External_MUX_Present 1 . nInTimer::tInTimer_External_MUX_Present_t @ This bit determines when the AI_LOCALMUX_CLK output signal pulses: @ This bit allows you to use the AI_DIV counter for AI_LOCALMUX_CLK @ signal control. This is useful if one or more external @ multiplexers, such as an AMUX-64T or SCXI, are connected @ to the board the STC3 is on. You should set this bit to @ 0 if no external multiplexers are present or if each external @ channel corresponds to one internal channel. You should set @ this bit to 1 if one or more external multiplexers are present @ and if you are multiplexing more than one external channel @ onto each internal channel. If this bit is set to 1, the @ AI_DIV counter must be used to determine the number of AI_EXTMUX_CLK @ pulses that correspond to one AI_LOCALMUX_CLK pulse. F Pre_Trigger 1 . nInTimer::tInTimer_Pre_Trigger_t @ If AI_Continuous is 0, this bit selects between the posttrigger @ acquisition mode and the pretrigger acquisition mode: If @ AI_Continuous is 1, this bit is not used. F Start_Stop_Gate_Enable 1 . nInTimer::tInTimer_Disabled_Enabled_t @ This bit enables the start/stop gate (STST_GATE) When enabled, @ external AI_CONVERT pulses pass through the STC3 only during @ the interval between the assertion of AI_START and the assertion @ of AI_STOP. Only enable in the external AI_CONVERT mode. @ Disable this bitfield in the internal AI_CONVERT mode. F Reserved 1 F Trigger_Once 1 @ This bit controls the retriggerability of the AI_SC, AI_SI, AI_SI2 @ and AI_DIV counters:When this bit is 0, the counters @ remain armed and retriggerable after generating a timing @ sequence.
When the bit is 1, the counters disarm after @ one AI timing sequence
Set this bit to 0 for a single, @ finite-pretrigger-infinite-posttrigger AI operation. Set @ this bit to 1 if you would like to retrigger an acquisition.NOTE: @ If the operation is halted by AI_End_On_End_Of_Scan or AI_End_On_SC_TC, @ the counters are disarmed, regardless of the @ state of this bit.
F Continuous 1 @ This bit determines the behavior of the AI_SC, AI_SI, AI_SI2, @ and AI_DIV counters during SC_TC:If this bit is set to @ 0, when AI_Pre_Trigger is 0, the counters return to idle on @ the first SC_TC. If AI_Pre_Trigger is 1, the counters return @ to idle on the second SC_TC
If this bit is set to @ 1, the counters ignore SC_TC.
Set this bit to 0 if you wish @ to acquire a predetermined number of scans. You will also @ need to use AI_Pre_Trigger to select the pretrigger or posttrigger @ acquisition mode.value ='0' => Idle
value ='1' => Counting @
value ='2' => Waiting for AI_START
F Reserved 2 F SI_Q_St 2 @ This bitfield reflects the state of the AI_SI control state machine: @value ='0' => Idle
value ='1' => Waiting @ for AI_START
value ='2' => Counting
value @ ='3' => Counting Until TC
F Reserved 1 F DIV_Q_St 1 . nInTimer::tInTimer_Idle_Counting_t @ This bit reflects the state of the AI_DIV control state machine. F Reserved 16 #------------------------------------------------------------------------------- # Mode_2_Register Register Definition R Mode_2_Register 32 0x08 Writable F Reserved 5 F EXTMUX_CLK_Pulse_Width 1 . nInTimer::tInTimer_EXTMUX_CLK_Pulse_Width_t @ This bit selects the pulsewidth and assertion time of the AI_EXTMUX_CLK @ output signal: F Reserved 1 F EXTMUX_CLK_Polarity 1 . nInTimer::tInTimer_Polarity_t @ When AI_EXTMUX_CLK is output on a PFI pin, this bit enables and @ selects the polarity of the AI_EXTMUX_CLK output signal: F Reserved 1 F SCAN_IN_PROG_Polarity 1 . nInTimer::tInTimer_Polarity_t @ When AI_START is output on a PFI pin and AI_START_Output_Select @ is set to 1 (output SCAN_IN_PROG), this bitfield selects @ the polarity of the SCAN_IN_PROG signal F START_Output_Select 1 . nInTimer::tInTimer_START_Output_Select_t @ This bit selects the source for the AI_START signal output on @ PFI. F Reserved 6 F Start2_Export_Mode 1 . nInTimer::tInTimer_Start2_Export_Mode_t @ This bit determines the AI_START2 signal when it is output on @ one of the PFI pins. F Start1_Export_Mode 1 . nInTimer::tInTimer_Start1_Export_Mode_t @ This bit determines the AI_START1 signal when it is output on @ one of the PFI pins. F Start_Trigger_Length 1 . nInTimer::tInTimer_Start_Trigger_Length_t @ This bit determines the length of the AI_START signal when it @ is output on one of the PFI pins and AI_START_Output_Select @ is set to 0 (AI_START). F SyncMode 2 . nInTimer::tInTimer_SyncMode_t @ This bitfield determines the mode of operation of trigger synchronization. F FIFO_Mode 2 . nInTimer::tInTimer_FIFO_Mode_t @ This bit selects the AI data FIFO condition on which to generate @ the FIFO interrupt (if the FIFO interrupt is enabled) F External_Gate_Mode 1 . nInTimer::tInTimer_External_Gate_Mode_t @ This bit determines the gating mode, if gating is enabled. Refer @ to the Gating section for more information on gating modes. F Reserved 2 F SI2_Source_Select 1 . nInTimer::tInTimer_SI2_Source_Select_t @ This bit selects the AI_SI2 source. In MIO mode, the AI_SI2 signal @ will clock the SI2 counter and in internal timing, it @ will generate the convert signal. F Reserved 1 F Software_Gate 1 @ This bit controls the software gate, which you can use to pause @ an analog input operation:value ='0' => Enable operation @
value ='1' => Pause operation
Refer to the @ Gating section for more information on software gating. F HaltOnError 1 @ When set, the timing engine will prevent any more converts to @ be generated or any more data to be written to the FIFO after @ an error condition. F Reserved 1 #------------------------------------------------------------------------------- # SI_Save_Register Register Definition R SI_Save_Register 32 0x08 Readable F SI_Save_Value 32 @ This bitfield reflects the contents of the AI_SI counter. Reading @ from this bitfield while the AI_SI counter is counting @ may result in an erroneous value. #------------------------------------------------------------------------------- # SC_Save_Register Register Definition R SC_Save_Register 32 0x0C Readable F SC_Save_Value 32 @ Reflects the state of the SC counter. IT is a safe read even @ when the counter is running. #------------------------------------------------------------------------------- # SI_Load_A_Register Register Definition R SI_Load_A_Register 32 0x0C Writable F SI_Load_A 32 @ This bitfield is the load value A for the AI_SI counter. If load @ register A is the selected AI_SI load register, the AI_SI @ counter loads the value contained in this bitfield on AI_SI_Load @ and on SI_TC. CAUTION : To prevent register @ ready violations, this register should be written only once @ before the value is loaded via AI_SI_Load (in the Command @ register). #------------------------------------------------------------------------------- # SI2_Save_Register Register Definition R SI2_Save_Register 32 0x10 Readable F SI2_Save_Value 32 @ This bitfield reflects the contents of the AI_SI2 counter. Reading @ from this bitfield while the AI_SI2 counter is counting @ may result in an erroneous value. #------------------------------------------------------------------------------- # SI_Load_B_Register Register Definition R SI_Load_B_Register 32 0x10 Writable F SI_Load_B 32 @ This bitfield is the load value B for the AI_SI counter. If load @ register B is the selected AI_SI load register, the AI_SI @ counter loads the value contained in this bitfield on AI_SI_Load @ and on SI_TC. CAUTION : To prevent register @ ready violations, this register should be written only once @ before the value is loaded via AI_SI_Load (in the Command @ register). #------------------------------------------------------------------------------- # DIV_Save_Register Register Definition R DIV_Save_Register 16 0x14 Readable F DIV_Save_Value 16 @ This bitfield reflects the contents of the AI_DIV counter. Reading @ from this bitfield while the AI_DIV counter is counting @ may result in an erroneous value. #------------------------------------------------------------------------------- # SC_Load_A_Register Register Definition R SC_Load_A_Register 32 0x14 Writable F SC_Load_A 32 @ This bitfield is the load value A for the AI_SC counter. If load @ register A is the selected AI_SC load register, the AI_SC @ counter loads the value contained in this bitfield on AI_SC_Load @ and on SC_TC. CAUTION : To prevent register @ ready violations, this register should be written only once @ before the value is loaded via AI_SC_Load (in the Command @ register). #------------------------------------------------------------------------------- # SC_Load_B_Register Register Definition R SC_Load_B_Register 32 0x18 Writable F SC_Load_B 32 @ This bitfield is the load value B for the AI_SC counter. If load @ register B is the selected AI_SC load register, the AI_SC @ counter loads the value contained in this bitfield on AI_SC_Load @ and on SC_TC. CAUTION : To prevent register @ ready violations, this register should be written only once @ before the value is loaded via AI_SC_Load (in the Command @ register). #------------------------------------------------------------------------------- # SC_PreWaitCntRegister Register Definition R SC_PreWaitCntRegister 32 0x18 Readable F SC_PreWaitCount 32 @ This register reflects the number of points that were acquired @ between the end of the pre-trigger count of samples and the @ arrival of the START2 trigger. This register should be read @ after the START2 trigger (at the end of the acquisition, for @ example). For very long (more than 2^32 samples in the Waiting @ state) acquisitions, SW needs to keep track of the DI_SC_PreWaitCountTC @ event in order to keep an accurate count. #------------------------------------------------------------------------------- # SI2_Load_A_Register Register Definition R SI2_Load_A_Register 32 0x1c Writable F SI2_Load_A 32 @ This bitfield is the load value A for the AI_SI2 counter. If @ load register A is the selected AI_SI2 load register, the AI_SI2 @ counter loads the value contained in this bitfield on AI_SI2_Load @ and on SI2_TC. CAUTION : To prevent register @ ready violations, this register should be written only @ once before the value is loaded via AI_SI_Load (in the Command @ register). #------------------------------------------------------------------------------- # SI2_Load_B_Register Register Definition R SI2_Load_B_Register 32 0x20 Writable F SI2_Load_B 32 @ This bitfield is the load value B for the AI_SI2 counter. If @ load register B is the selected AI_SI2 load register, the AI_SI2 @ counter loads the value contained in this bitfield on AI_SI2_Load @ and on SI2_TC. CAUTION : To prevent register @ ready violations, this register should be written only @ once before the value is loaded via AI_SI2_Load (in the Command @ register). #------------------------------------------------------------------------------- # DIV_Load_A_Register Register Definition R DIV_Load_A_Register 16 0x24 Writable F DIV_Load_A 16 @ This bitfield is the load register for the AI_DIV counter. The @ AI_DIV counter loads the value contained in this bitfield @ on AI_DIV_Load and on DIV_TC. The DIV Counter can be used to @ repeat N times each entry in the configuration FIFO, where @ N is the value programmed in this register. #------------------------------------------------------------------------------- # Interrupt1_Register Register Definition R Interrupt1_Register 32 0x2C Writable --no-soft-copy true F SC_TC_Interrupt_Enable 1 Strobe @ This strobe bit enables the SC_TC interrupt: SC_TC interrupts @ are generated on every SC_TC falling edge unless the pretrigger @ acquisition mode is selected. In the pretrigger acquisition @ mode, the first SC_TC falling edge does not generate an @ interrupt, but subsequent SC_TC falling edges do. F START1_Interrupt_Enable 1 Strobe @ This strobe bit enables the AI_START1 interrupt: The AI_START1 @ interrupt is generated on valid AI_START1 triggers received @ by the STC3. A valid AI_START1 trigger is one that is received @ while the AI_SC counter is armed and in the Idle state. F START2_Interrupt_Enable 1 Strobe @ This strobe bit enables the AI_START2 interrupt: The AI_START2 @ interrupt is generated on valid AI_START2 triggers received @ by the STC3. A valid AI_START2 trigger is one that is received @ while the AI_SC counter is in the Waiting for AI_START2 @ state. F START_Interrupt_Enable 1 Strobe @ This strobe bit enables the AI_START interrupt: The AI_START @ interrupt is generated on valid AI_START triggers received by @ the STC3. A valid AI_START trigger is one that is received @ while the AI_SC counter is enabled to count. F STOP_Interrupt_Enable 1 Strobe @ This strobe bit enables the AI_STOP interrupt: The AI_STOP interrupt @ is generated on valid AI_STOP triggers recognized by @ the STC3. A valid AI_STOP trigger is one that is received while @ the AI_SC counter is enabled to count after a valid AI_START. F Overrun_Interrupt_Enable 1 Strobe @ This strobe bit enables the AI Overrun interrupt: F Overflow_Interrupt_Enable 1 Strobe @ This strobe bit enables the AI Overflow interrupt: F FIFO_Interrupt_Enable 1 Strobe @ This strobe bit enables the AI FIFO interrupt: The FIFO interrupt @ is generated on the FIFO condition indicated by AI_FIFO_Mode. F ScanOverrun_Interrupt_Enable 1 Strobe @ This strobe bit enables the AI ScanOverrun interrupt: A ScanOverrun @ error is generated if an AI sample clock pulse comes @ in the middle of a scan interval (time between the sample clock @ and the convert pulse of the last channel for that sample). F SC_PreWaitCountTC_Interrupt_Enable 1 Strobe @ This bit enables the Interrupt on the event that the SC_TC rolls @ over when the device is in the PreWait state. This is the state @ after the pretrigger count has been satisfied but before the @ START2 trigger has been received. This event is useful to @ keep track of how many points have been received. If another @ of these events happens before the original is acknowledged @ the error will be signaled by the SC_PreWaitCountTC_ErrorSt @ bit F Reserved 12 F ScanOverrun_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AI_ScanOverrun_St. This bit is cleared @ automatically. F SC_TC_Error_Confirm 1 Strobe @ Setting this bit to 1 clears AI_SC_TC_Error_St. This bit is cleared @ automatically. F SC_TC_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AI_Last_Shiftin_St, AI_SC_TC_St, @ and the SC_TC interrupt request (in either interrupt bank) @ if the SC_TC interrupt is enabled. This bit is cleared automatically. F START1_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AI_START1_St and acknowledges the @ AI_START1 interrupt request if the AI_START1 interrupt is @ enabled. This bit is cleared automatically. F START2_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AI_START2_St and acknowledges the @ AI_START2 interrupt request if the AI_START2 interrupt is @ enabled. This bit is cleared automatically. F START_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AI_START_St and acknowledges the @ AI_START interrupt request if the AI_START interrupt is enabled. @ This bit is cleared automatically. F STOP_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AI_STOP_St and acknowledges the @ AI_STOP interrupt request if the AI_STOP interrupt is enabled. @ This bit is cleared automatically. F Overrun_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AI_Overrun_St and acknowledges the @ Overrun interrupt request if the Overrun interrupt is enabled. @ This bit is cleared automatically. F SC_PreWaitCountTC_Interrupt_Ack 1 Strobe @ This bit clears the SC_PreWaitCountTC_Interrupt event and acknowledges @ the interrupt. F Overflow_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears AI_Overflow_St and acknowledges @ the Overflow interrupt request if the Overflow interrupt is @ enabled. This bit is cleared automatically. #------------------------------------------------------------------------------- # Interrupt2_Register Register Definition R Interrupt2_Register 32 0x30 Writable --no-soft-copy true F SC_TC_Interrupt_Disable 1 Strobe @ This bit disables the SC_TC interrupt. SC_TC interrupts are generated @ on every SC_TC falling edge unless the pretrigger acquisition @ mode is selected. In the pretrigger acquisition mode, @ the first SC_TC falling edge does not generate an interrupt, @ but subsequent SC_TC falling edges do. F START1_Interrupt_Disable 1 Strobe @ This bit disables the AI_START1 interrupt. The AI_START1 interrupt @ is generated on valid AI_START1 triggers received by the @ STC3. A valid AI_START1 trigger is one that is received while @ the AI_SC counter is armed and in the Idle state. F START2_Interrupt_Disable 1 Strobe @ This bit disables the AI_START2 interrupt. The AI_START2 interrupt @ is generated on valid AI_START2 triggers received by the @ STC3. A valid AI_START2 trigger is one that is received while @ the AI_SC counter is in the Waiting for AI_START2 state. F START_Interrupt_Disable 1 Strobe @ This bit disables the AI_START interrupt. The AI_START interrupt @ is generated on valid AI_START triggers received by the STC3. @ A valid AI_START trigger is one that is received while the @ AI_SC counter is enabled to count. F STOP_Interrupt_Disable 1 Strobe @ This bit disables the AI_STOP interrupt. The AI_STOP interrupt @ is generated on valid AI_STOP triggers recognized by the STC3. @ A valid AI_STOP trigger is one that is received while the @ AI_SC counter is enabled to count after a valid AI_START. F Overrun_Interrupt_Disable 1 Strobe @ This strobe bit disables the AI Overrun interrupt. F Overflow_Interrupt_Disable 1 Strobe @ This strobe bit disables the AI Overflow interrupt. F FIFO_Interrupt_Disable 1 Strobe @ This bit disables the AI FIFO interrupt: The FIFO interrupt is @ generated on the FIFO condition indicated by AI_FIFO_Mode. F ScanOverrun_Interrupt_Disable 1 Strobe @ This bit disables the AI ScanOverrun interrupt: A ScanOverrun @ error is generated if an AI sample clock pulse comes in the @ middle of a scan interval (time between the sample clock and @ the convert pulse of the last channel for that sample). F SC_PreWaitCountTC_Interrupt_Disable 1 Strobe @ This bit disables the Interrupt on the event that the SC_TC rolls @ over when the device is in the PreWait state. This is the state @ after the pretrigger count has been satisfied but before the @ START2 trigger has been received. This event is useful to @ keep track of how many points have been received. If another @ of these events happens before the original is acknowledged @ the error will be signaled by the SC_PreWaitCountTC_ErrorSt @ bit F Reserved 12 F ScanOverrun_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AI_ScanOverrun_St. This bit is cleared @ automatically. F SC_TC_Error_Confirm2 1 Strobe @ Setting this bit to 1 clears AI_SC_TC_Error_St. This bit is cleared @ automatically. F SC_TC_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AI_Last_Shiftin_St, AI_SC_TC_St, @ and the SC_TC interrupt request if the SC_TC interrupt is enabled. @ This bit is cleared automatically. F START1_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AI_START1_St and acknowledges the @ AI_START1 interrupt request if the AI_START1 interrupt is @ enabled. This bit is cleared automatically. F START2_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AI_START2_St and acknowledges the @ AI_START2 interrupt request if the AI_START2 interrupt is @ enabled. This bit is cleared automatically. F START_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AI_START_St and acknowledges the @ AI_START interrupt request if the AI_START interrupt is enabled. @ This bit is cleared automatically. F STOP_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AI_STOP_St and acknowledges the @ AI_STOP interrupt request if the AI_STOP interrupt is enabled. @ This bit is cleared automatically. F Overrun_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AI_Overrun_St and acknowledges the @ Overrun interrupt request if the Overrun interrupt is enabled. @ This bit is cleared automatically. F SC_PreWaitCountTC_Interrupt_Ack2 1 Strobe @ This bit clears the SC_PreWaitCountTC_Interrupt event and acknowledges @ the interrupt. F Overflow_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears AI_Overflow_St and acknowledges @ the Overflow interrupt request if the Overflow interrupt is @ enabled. This bit is cleared automatically. #------------------------------------------------------------------------------- # Reset_Register Register Definition R Reset_Register 16 0x38 Writable --no-soft-copy true F Reset 1 Strobe @ NOTE Using this bitfield to reset the timer will also @ activate the ConfigReset. A strobe write to the Configuration_End @ bitfield must be executed after reseting the timer with @ this bitfield. (In a separate register access).