#****************************************************************************** # DMAController.rbm # # (c) Copyright 2011 # National Instruments Corporation. # All rights reserved. # License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT # Refer to "MHDDK License Agreement.pdf" in the root of this distribution. # # Description: # rbm file for the CHInCh DMA Controller. # This file is autogenerated. Do not modify it directly. # # All lines starting with # or C are comments # All lines starting with T define a register Type # All lines starting with TR define register name, type, offset # All lines starting with F are Fields within the preceding register, # Its name, size, attribute (Strobe|.) and type are defined. # #****************************************************************************** # Declaring RBM as a containable chip object. # This means all instances must specify an offset for it. --containable #=============================================================================== # Register Group Enumerated_Types #=============================================================================== #------------------------------------------------------------------------------- # Enumerated type DMA_Mode_t #------------------------------------------------------------------------------- E DMA_Mode_t V NormalDmaMode 1 V LinkChainDmaMode 2 #=============================================================================== # Register Group CHInCh DMA Controller #=============================================================================== #------------------------------------------------------------------------------- # Channel_Memory_Address_Register Register Definition R Channel_Memory_Address_Register_LSW 32 0x38 Readable|Writable --force-default true --no-soft-copy true F Memory_Address_LSW 32 @ For Normal mode (NormalDmaMode), this field stores the @ address location of the next DMA data to transfer on the host bus. @ This is used in both modes. In Link Chaining mode, it is not @ necessary to initialize this field since the Link process will @ do so. When the DMA_MA64 bit in the Host Bus Resource Control @ Register (HBRCR) is clear, it is not necessary to write the @ upper half of this register. The value returned when reading @ this register is not guaranteed to be coherent with DMA data @ transfers. This field resets to an unknown value. When writing @ to this register using 8-bit writes, software must start with @ the least significant byte and must write at least 3 bytes. R Channel_Memory_Address_Register_MSW 32 0x3C Readable|Writable --force-default true --no-soft-copy true F Memory_Address_MSW 32 @ This 64-bit register has been divided into two 32-bit registers @ to support those architectures. 64-bit architectures can access @ the register atomically. #------------------------------------------------------------------------------- # Channel_Link_Address_Register Register Definition R Channel_Link_Address_Register_LSW 32 0x48 Readable|Writable --force-default true --no-soft-copy true F Reserved 3 F Link_Address_LSW 29 @ For Link Chain mode (LinkChainDmaMode), this field stores the address @ location of the next DMA link to be fetched. This is only used in @ Link Chaining mode. This field should be initialized to point to @ the first DMA link before the START bit is written with a 1 in @ the Channel Operation Register (CHOR). When the DMA_LA64 bit in @ the Host Bus Resource Control Register (HBRCR) is clear, it is not @ necessary to write the upper half of this register. The link @ processor updates this field as links are processed. Note that @ this register only accepts values that are naturally aligned to 8 @ bytes. This field resets to an unknown value. R Channel_Link_Address_Register_MSW 32 0x4C Readable|Writable --force-default true --no-soft-copy true F Link_Address_MSW 32 @ This 64-bit register has been divided into two 32-bit registers @ to support those architectures. 64-bit architectures can access @ the register atomically. #------------------------------------------------------------------------------- # Channel_Link_Size_Register Register Definition R Channel_Link_Size_Register 32 0x50 Readable|Writable --force-default true --no-soft-copy true F Reserved 3 F Link_Size 29 @ This field stores the size of the next DMA link to be fetched. This is @ only used in Link Chaining mode. This field should be initialized to @ the size of the first DMA link before the START bit is written with a 1 @ in the Channel Operation Register (CHOR). The link processor updates this @ field as links are processed. Note that this register only accepts values @ that are integer multiples of 8 bytes. This field resets to an unknown value. #------------------------------------------------------------------------------- # Channel_Control_Register Register Definition R Channel_Control_Register 32 0x54 Readable|Writable --no-hardware-reset true --force-default true F MODE 2 . nDMAController::tDMA_Mode_t @ This field controls the DMA mode. This field resets to an unknown value. F Reserved 6 F Reserved 2 F Reserved 1 F Reserved 1 F Reserved 1 F Reserved 1 F Reserved 1 F Notify_On_Done 1 @ Setting this bit causes the DMA channel to generate an interrupt when the @ Done bit in the Channel Status Register (CHSR) changes from 0 to 1. Writing a @ 0 to this bit will also clear the Done bit in the Channel Status Register (CHSR) @ so that the interrupt condition will not be reported when it is disabled. This bit @ resets to an unknown value. F Reserved 2 F Reserved 1 F Reserved 1 F Reserved 2 F Reserved 1 F Reserved 1 F Reserved 1 F Notify_On_Total_Count 1 @ Setting this bit causes the DMA channel to generate an interrupt when the @ Total_Count bit in the Channel Status Register (CHSR) changes from 0 to 1. @ Writing a 0 to this bit will also clear the Total_Count bit in the Channel Status @ Register (CHSR) so that the interrupt condition will not be reported when it is @ disabled. This bit resets to an unknown value. F Notify_On_Last_Link 1 @ Setting this bit causes the DMA channel to generate an interrupt after @ processing the last link of a chain. Writing a 0 to this bit will also clear the Last @ Link bit in the Channel Status Register (CHSR) so that the interrupt condition @ will not be reported when it is disabled. This bit resets to an unknown value. F Notify_On_Error 1 @ Setting this bit causes the DMA channel to generate interrupts when errors @ are encountered during DMA operations. Writing a 0 to this bit will also clear @ the Error bit in the Channel Status Register (CHSR) so that the interrupt @ condition will not be reported when it is disabled. This bit resets to an unknown @ value. F Reserved 4 #------------------------------------------------------------------------------- # Channel_Operation_Register Register Definition R Channel_Operation_Register 32 0x58 Readable|Writable --no-hardware-reset true --force-default true F START 1 @ Writing a 1 to this bit starts the DMA channel. Once the DMA channel is started, @ DMA requests from the Stream Circuit the corresponding stream will be serviced. @ Starting a DMA channel will also cause link fetching to begin if using Link @ Chaining mode. Writing a 1 to this bit also clears all interrupt conditions in @ the Channel Status Register (CHSR). The interrupt conditions can be cleared by @ writing a 1 to this bit even if the DMA channel is already started. Reading this @ bit returns 1 when the DMA channel is started and 0 when it is stopped. On reset, @ the state of Start is unknown and the DMA channel must be stopped and then started @ before it is operational. Except for the first use of a DMA channel, Start should @ not be written with a 1 until one of the Error, Last_Link, or Done bits of the Channel @ Status Register (CHSR) returns 1. F STOP 1 @ Writing a 1 to this bit stops the DMA channel. The STOP bit will take priority @ when both the START and STOP bits are set in the same write. Reading this bit returns @ 0 when the DMA channel is started and 1 when it is stopped. F CLR_TTC 1 @ Writing a 1 to this bit clears the Channel Total Transfer Count Status Register @ (CHTTCSR). Note that this bit can be written with a 1 in the same register @ access that the START bit is written with a 1. It is not necessary to clear this bit @ after setting it. This bit returns 0 when read. F Reserved 1 F Reserved 20 F Reserved 1 F Arm_Total_Count_Int 1 @ Writing a 1 to this bit arms the total transfer count interrupt for the byte count @ specified in the Channel Total Transfer Count Compare Register (CHTTCCR). @ If the Channel Total Transfer Count Status Register (CHTTCSR) has already been @ reached or passed the specified byte count the interrupt will occur immediately @ when this bit is written with a 1. It is not necessary to clear this bit after setting @ it. When read, this bit indicates if a Total Transfer Count interrupt is currently @ armed. The interrupt will be armed from the time this bit is written with a 1 @ until the interrupt occurs. The behavior is undefined if this bit is written with a @ 1 in the same register access that any of the CLR_TTC, STOP, or START bits @ are written with a 1. F Reserved 6 #------------------------------------------------------------------------------- # Channel_Status_Register Register Definition R Channel_Status_Register 32 0x60 Readable --no-soft-copy true F STREAM 12 @ This read-only field returns the Stream Circuit number that the DMA channel is @ associated with. F Reserved 1 F Reserved 1 F Link_Ready 1 @ This read-only bit returns a 1 when the DMA channel has a link that is ready to be @ processed. This status could be useful for optimizing the start-up of an acquisition @ or generation operation. Some applications might need to hold off acquisition or @ generation until the DMA channel has fetched a link. F Done 1 @ This read-only bit indicates that the DMA operation has ended due to the receipt @ of a Done indication from the associated subsystem or because the Stop bit in the @ Channel Operation Register (CHOR) was written with a 1. The conditions that @ set this bit also cause the DMA channel to be stopped in the Channel Operation @ Register (CHOR). An interrupt will also be generated when this bit sets if the @ Notify_On_Done bit of the Channel Control Register (CHCR) is set. The value @ of this bit is unknown on reset but clears when the START bit in the Channel @ Operation Register (CHOR) is written with a 1. This bit also clears when read @ from the volatile offset and when the Notify_On_Done bit in the Channel Control @ Register (CHCR) is written with a 0. Once this bit is set, it is safe to free system @ memory buffers that are used to store the application data and linked-list. It is @ also safe to start a new operation on the DMA channel once this bit sets. F Reserved 8 F Reserved 1 F Total_Count 1 @ After having been armed with the Arm_Total_Count_Int bit in the Channel @ Operation Register (CHOR), this read-only bit sets after the DMA channel @ transfers the data to or from host memory that causes the Channel Total Transfer @ Count Status Register (CHTTCSR) to reach or pass the value in the Channel @ Total Transfer Count Compare Register (CHTTCCR). An interrupt will also @ be generated when this bit sets if the Notify_On_Total_Count bit of the Channel @ Control Register (CHCR) is set. The value of this bit is unknown on reset but @ clears when the START bit in the Channel Operation Register (CHOR) is @ written with a 1. This bit also clears when read from the volatile offset and @ when the Notify_On_Total_Count bit in the Channel Control Register (CHCR) is @ written with a 0. Once this bit returns a 1, the application data represented by the @ value in the Channel Total Transfer Count Compare Register (CHTTCCR) is @ guaranteed to have been moved to or from system memory. F Last_Link 1 @ This read-only bit sets after the linked-list has been fully processed. This bit sets @ after the DMA channel transfers the data of the last page descriptor in a chain to @ or from host memory. The conditions that set this bit also cause the DMA channel to @ be stopped in the Channel Operation Register (CHOR). An interrupt will also be generated @ when this bit sets if the Notify_ On_Last_Link bit of the Channel Control Register (CHCR) @ is set. The value of this bit is unknown on reset but clears when the START bit @ in the Channel Operation Register (CHOR) is written with a 1. This bit also @ clears when read from the volatile offset and when the Notify_On_Last_Link bit @ in the Channel Control Register (CHCR) is written with a 0. Once this bit is set @ it is safe to free system memory buffers that are used to store the application @ data and linked-list. It is also safe to start a new operation on the DMA @ channel once this bit sets. Note that the Last_Link bit can return an invalid @ value when the Done bit in this register is set. Software should ignore the @ Last_Link bit when the Done bit is set. F Error 1 @ This read-only bit sets when the DMA channel experiences an error condition @ while accessing host memory. This will also cause the DMA channel to be @ stopped in the Channel Operation Register (CHOR). An interrupt will also be @ generated when this bit sets if the Notify_On_Error bit of the Channel Control @ Register (CHCR) is set. The value of this bit is unknown on reset but clears @ when the START bit in the Channel Operation Register (CHOR) is written with @ a 1. This bit also clears when read from the volatile offset and when the Notify_ @ On_Error bit in the Channel Control Register (CHCR) is written with a 0. Once @ this bit is set it is safe to free system memory buffers that are used to store the @ application data and linked-list. It is also safe to start a new operation on the @ DMA channel once this bit sets. F Reserved 2 F Additional_Int 1 @ This read-only bit returns 0 when read from the Channel Status Register (CHSR) or @ Channel Volatile Status Register (CHVSR). This bit is only effective when read from @ the Interrupt Status Register (ISR) or Volatile Interrupt Status Register (VISR). F Int 1 @ This read-only bit returns 1 when the DMA channel has a pending interrupt. @ This bit will clear when read from the volatile offset because all interrupt @ conditions are also in this register. #------------------------------------------------------------------------------- # Channel_Volatile_Status_Register Register Definition R Channel_Volatile_Status_Register 32 0x68 Readable --no-soft-copy true F Vol_STREAM 12 @ This read-only field returns the Stream Circuit number that the DMA channel is @ associated with. F Reserved 1 F Reserved 1 F Vol_Link_Ready 1 @ This read-only bit returns a 1 when the DMA channel has a link that is ready to be @ processed. This status could be useful for optimizing the start-up of an acquisition @ or generation operation. Some applications might need to hold off acquisition or @ generation until the DMA channel has fetched a link. F Vol_Done 1 @ This read-only bit indicates that the DMA operation has ended due to the receipt @ of a Done indication from the associated subsystem or because the Stop bit in the @ Channel Operation Register (CHOR) was written with a 1. The conditions that @ set this bit also cause the DMA channel to be stopped in the Channel Operation @ Register (CHOR). An interrupt will also be generated when this bit sets if the @ Notify_On_Done bit of the Channel Control Register (CHCR) is set. The value @ of this bit is unknown on reset but clears when the START bit in the Channel @ Operation Register (CHOR) is written with a 1. This bit also clears when read @ from the volatile offset and when the Notify_On_Done bit in the Channel Control @ Register (CHCR) is written with a 0. Once this bit is set, it is safe to free system @ memory buffers that are used to store the application data and linked-list. It is @ also safe to start a new operation on the DMA channel once this bit sets. F Reserved 8 F Reserved 1 F Vol_Total_Count 1 @ After having been armed with the Arm_Total_Count_Int bit in the Channel @ Operation Register (CHOR), this read-only bit sets after the DMA channel @ transfers the data to or from host memory that causes the Channel Total Transfer @ Count Status Register (CHTTCSR) to reach or pass the value in the Channel @ Total Transfer Count Compare Register (CHTTCCR). An interrupt will also @ be generated when this bit sets if the Notify_On_Total_Count bit of the Channel @ Control Register (CHCR) is set. The value of this bit is unknown on reset but @ clears when the START bit in the Channel Operation Register (CHOR) is @ written with a 1. This bit also clears when read from the volatile offset and @ when the Notify_On_Total_Count bit in the Channel Control Register (CHCR) is @ written with a 0. Once this bit returns a 1, the application data represented by the @ value in the Channel Total Transfer Count Compare Register (CHTTCCR) is @ guaranteed to have been moved to or from system memory. F Vol_Last_Link 1 @ This read-only bit sets after the linked-list has been fully processed. This bit sets @ after the DMA channel transfers the data of the last page descriptor in a chain to @ or from host memory. The conditions that set this bit also cause the DMA channel to @ be stopped in the Channel Operation Register (CHOR). An interrupt will also be generated @ when this bit sets if the Notify_ On_Last_Link bit of the Channel Control Register (CHCR) @ is set. The value of this bit is unknown on reset but clears when the START bit @ in the Channel Operation Register (CHOR) is written with a 1. This bit also @ clears when read from the volatile offset and when the Notify_On_Last_Link bit @ in the Channel Control Register (CHCR) is written with a 0. Once this bit is set @ it is safe to free system memory buffers that are used to store the application @ data and linked-list. It is also safe to start a new operation on the DMA @ channel once this bit sets. Note that the Last_Link bit can return an invalid @ value when the Done bit in this register is set. Software should ignore the @ Last_Link bit when the Done bit is set. F Vol_Error 1 @ This read-only bit sets when the DMA channel experiences an error condition @ while accessing host memory. This will also cause the DMA channel to be @ stopped in the Channel Operation Register (CHOR). An interrupt will also be @ generated when this bit sets if the Notify_On_Error bit of the Channel Control @ Register (CHCR) is set. The value of this bit is unknown on reset but clears @ when the START bit in the Channel Operation Register (CHOR) is written with @ a 1. This bit also clears when read from the volatile offset and when the Notify_ @ On_Error bit in the Channel Control Register (CHCR) is written with a 0. Once @ this bit is set it is safe to free system memory buffers that are used to store the @ application data and linked-list. It is also safe to start a new operation on the @ DMA channel once this bit sets. F Reserved 2 F Vol_Additional_Int 1 @ This read-only bit returns 0 when read from the Channel Status Register (CHSR) or @ Channel Volatile Status Register (CHVSR). This bit is only effective when read from @ the Interrupt Status Register (ISR) or Volatile Interrupt Status Register (VISR). F Vol_Int 1 @ This read-only bit returns 1 when the DMA channel has a pending interrupt. @ This bit will clear when read from the volatile offset because all interrupt @ conditions are also in this register. #------------------------------------------------------------------------------- # Channel_Total_Transfer_Count_Compare_Register Register Definition R Channel_Total_Transfer_Count_Compare_Register_LSW 32 0x90 Readable|Writable --no-soft-copy true --force-default true F TCC_LSW 32 @ This register specifies a total byte count at which an interrupt is desired. This @ entire register should be at the desired value before the interrupt is armed in the @ Channel Operation Register (CHOR). After being armed, the interrupt will occur @ once the Channel Total Transfer Count Status Register (CHTTCSR) reaches or @ passes the programmed value. When any byte of this register is written, the @ interrupt is disarmed. This prevents a bad comparison from occurring when @ multiple writes are required to provide the whole value. If a previous value had @ been armed, writing a new value to this register disarms it. A write to any byte @ of this register also clears the Total_Count bit of the Channel Status Register @ (CHSR). Note that the previously armed value might have triggered an interrupt @ just before it gets disarmed by a write of the new value to this register. Clearing @ the Total_Count status bit on any write of this field prevents software from @ seeing an interrupt condition from any previously armed value. This field resets @ to an unknown value so it should be initialized before the interrupt is armed. R Channel_Total_Transfer_Count_Compare_Register_MSW 32 0x94 Readable|Writable --no-soft-copy true --force-default true F TCC_MSW 32 @ This 64-bit register has been divided into two 32-bit regsiters @ to support those architectures. 64-bit architectures can access @ the register atomically. #------------------------------------------------------------------------------- # Channel_Total_Transfer_Count_Status_Register Register Definition R Channel_Total_Transfer_Count_Status_Register_LSW 32 0xA0 Readable --no-soft-copy true F TTCS_LSW 32 @ This read-only field indicates the total number of bytes that have been @ transferred to or from host memory by the DMA channel since the last time the @ CLR_TTC bit in the Channel Operation Register (CHOR) was written with a 1. @ Reads of this register are coherent with DMA data transfers – any data reported @ as moved by this register is guaranteed to have moved to or from system @ memory by the time software could act on the status. Assuming a system data @ width of 64-bits at a system clock rate of 133 MHz, this register represents over @ 548 years of uninterrupted data transfer. Note that special measures will be @ required to read an atomic value from the register with a processor that can't @ perform a 64-bit operation. In such a situation, software might read the upper @ half, then the lower half, then the upper half again. If the upper half changed @ between the two reads, software could safely use the larger value and assume a @ value of 0 for the lower half. Another option is to use the latching version of the @ register described below. Note also that this field resets to an unknown value, so @ it should be cleared with the CLR_TTC bit before use. R Channel_Total_Transfer_Count_Status_Register_MSW 32 0xA4 Readable --no-soft-copy true F TTCS_MSW 32 @ This 64-bit register has been divided into two 32-bit registers @ to support those architectures. 64-bit architectures can access @ the register atomically. #------------------------------------------------------------------------------- # Channel_Total_Transfer_Count_Latching_Register Register Definition R Channel_Total_Transfer_Count_Latching_Register_LSW 32 0xA8 Readable --no-soft-copy true F TTCL_LSW 32 @ This read-only field provides the same status as the previous register except it @ provides a latch for half the register so that 32-bit processors can read the value @ this register with a 32-bit access will @ return the value of the upper half at the time of the last read of the lower half. @ This allows processors that can't perform 64-bit accesses to read the 64-bit value @ without concern that it will change between reads. Note that multiple software @ threads cannot reliably access the same channel's Total Transfer Count Latching @ Register unless a mutex is used. R Channel_Total_Transfer_Count_Latching_Register_MSW 32 0xAC Readable --no-soft-copy true F TTCL_MSW 32 @ This 64-bit register has been divided into two 32-bit registers @ to support those architectures. 64-bit architectures can access @ the register atomically.