#******************************************************************************
# DI.rbm
#
# (c) Copyright 2011
# National Instruments Corporation.
# All rights reserved.
# License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT
# Refer to "MHDDK License Agreement.pdf" in the root of this distribution.
#
# Description:
# rbm file for DI.
# This file is autogenerated. Do not modify it directly.
#
# All lines starting with # or C are comments
# All lines starting with T define a register Type
# All lines starting with TR define register name, type, offset
# All lines starting with F are Fields within the preceding register,
# Its name, size, attribute (Strobe|.) and type are defined.
#
#******************************************************************************
# Declaring RBM as a containable chip object.
# This means all instances must specify an offset for it.
--containable
# Specify the location of the contained InTimer object
# contained within the DI engine.
--contains DI_Timer 0x30 InTimer.rbm "tInTimer.h"
--generate-include "tDIValues.h"
#===============================================================================
# Register Group Enumerated_Types
#===============================================================================
#-------------------------------------------------------------------------------
# Enumerated type DI_DataWidth_t
#-------------------------------------------------------------------------------
E DI_DataWidth_t
V DI_OneByte 0
V DI_TwoBytes 1
V DI_FourBytes 2
#-------------------------------------------------------------------------------
# Enumerated type DI_Data_Lane_t
#-------------------------------------------------------------------------------
E DI_Data_Lane_t
V DI_DataLane0 0
V DI_DataLane1 1
V DI_DataLane2 2
V DI_DataLane3 3
#-------------------------------------------------------------------------------
# Enumerated type DI_External_Gate_Select_t
#-------------------------------------------------------------------------------
E DI_External_Gate_Select_t
V Gate_Disabled 0
V Gate_PFI0 1
V Gate_PFI1 2
V Gate_PFI2 3
V Gate_PFI3 4
V Gate_PFI4 5
V Gate_PFI5 6
V Gate_PFI6 7
V Gate_PFI7 8
V Gate_PFI8 9
V Gate_PFI9 10
V Gate_RTSI0 11
V Gate_RTSI1 12
V Gate_RTSI2 13
V Gate_RTSI3 14
V Gate_RTSI4 15
V Gate_RTSI5 16
V Gate_RTSI6 17
V Gate_PXIe_DStarA 18
V Gate_PXIe_DStarB 19
V Gate_Star_Trigger 20
V Gate_PFI10 21
V Gate_PFI11 22
V Gate_PFI12 23
V Gate_PFI13 24
V Gate_PFI14 25
V Gate_PFI15 26
V Gate_RTSI7 27
V Gate_Analog_Trigger 30
V Gate_Low 31
V Gate_G0_Out 32
V Gate_G1_Out 33
V Gate_G2_Out 34
V Gate_G3_Out 35
V Gate_G0_Gate 36
V Gate_G1_Gate 37
V Gate_G2_Gate 38
V Gate_G3_Gate 39
V Gate_AI_Gate 40
V Gate_AO_Gate 43
V Gate_DO_Gate 44
V Gate_IntTriggerA0 53
V Gate_IntTriggerA1 54
V Gate_IntTriggerA2 55
V Gate_IntTriggerA3 56
V Gate_IntTriggerA4 57
V Gate_IntTriggerA5 58
V Gate_IntTriggerA6 59
V Gate_IntTriggerA7 60
#-------------------------------------------------------------------------------
# Enumerated type DI_FilterMode_t
#-------------------------------------------------------------------------------
E DI_FilterMode_t
V 6509Mode 0
V CorrelatedMode 1
#-------------------------------------------------------------------------------
# Enumerated type DI_Filter_Select_t
#-------------------------------------------------------------------------------
E DI_Filter_Select_t
V No_Filter 0
V Small_Filter 1
V Medium_Filter 2
V Large_Filter 3
#-------------------------------------------------------------------------------
# Enumerated type DI_Mask_t
#-------------------------------------------------------------------------------
E DI_Mask_t
V ForceZero 0
V KeepData 1
#-------------------------------------------------------------------------------
# Enumerated type DI_Polarity_t
#-------------------------------------------------------------------------------
E DI_Polarity_t
V Active_High_Or_Rising_Edge 0
V Active_Low_Or_Falling_Edge 1
#-------------------------------------------------------------------------------
# Enumerated type DI_START1_Select_t
#-------------------------------------------------------------------------------
E DI_START1_Select_t
V Start1_SW_Pulse 0
V Start1_PFI0 1
V Start1_PFI1 2
V Start1_PFI2 3
V Start1_PFI3 4
V Start1_PFI4 5
V Start1_PFI5 6
V Start1_PFI6 7
V Start1_PFI7 8
V Start1_PFI8 9
V Start1_PFI9 10
V Start1_RTSI0 11
V Start1_RTSI1 12
V Start1_RTSI2 13
V Start1_RTSI3 14
V Start1_RTSI4 15
V Start1_RTSI5 16
V Start1_RTSI6 17
V Start1_PXIe_DStarA 18
V Start1_PXIe_DStarB 19
V Start1_Star_Trigger 20
V Start1_PFI10 21
V Start1_PFI11 22
V Start1_PFI12 23
V Start1_PFI13 24
V Start1_PFI14 25
V Start1_PFI15 26
V Start1_RTSI7 27
V Start1_DIO_ChgDetect 28
V Start1_Analog_Trigger 30
V Start1_Low 31
V Start1_G0_Out 36
V Start1_G1_Out 37
V Start1_G2_Out 38
V Start1_G3_Out 39
V Start1_AI_Start1 40
V Start1_AO_Start1 43
V Start1_DO_Start1 44
V Start1_IntTriggerA0 53
V Start1_IntTriggerA1 54
V Start1_IntTriggerA2 55
V Start1_IntTriggerA3 56
V Start1_IntTriggerA4 57
V Start1_IntTriggerA5 58
V Start1_IntTriggerA6 59
V Start1_IntTriggerA7 60
#-------------------------------------------------------------------------------
# Enumerated type DI_START2_Select_t
#-------------------------------------------------------------------------------
E DI_START2_Select_t
V Start2_SW_Pulse 0
V Start2_PFI0 1
V Start2_PFI1 2
V Start2_PFI2 3
V Start2_PFI3 4
V Start2_PFI4 5
V Start2_PFI5 6
V Start2_PFI6 7
V Start2_PFI7 8
V Start2_PFI8 9
V Start2_PFI9 10
V Start2_RTSI0 11
V Start2_RTSI1 12
V Start2_RTSI2 13
V Start2_RTSI3 14
V Start2_RTSI4 15
V Start2_RTSI5 16
V Start2_RTSI6 17
V Start2_PXIe_DStarA 18
V Start2_PXIe_DStarB 19
V Start2_Star_Trigger 20
V Start2_PFI10 21
V Start2_PFI11 22
V Start2_PFI12 23
V Start2_PFI13 24
V Start2_PFI14 25
V Start2_PFI15 26
V Start2_RTSI7 27
V Start2_DIO_ChgDetect 28
V Start2_Analog_Trigger 30
V Start2_Low 31
V Start2_G0_Out 36
V Start2_G1_Out 37
V Start2_G2_Out 38
V Start2_G3_Out 39
V Start2_AI_Start2 40
V Start2_AO_Start1 43
V Start2_DO_Start1 44
V Start2_IntTriggerA0 53
V Start2_IntTriggerA1 54
V Start2_IntTriggerA2 55
V Start2_IntTriggerA3 56
V Start2_IntTriggerA4 57
V Start2_IntTriggerA5 58
V Start2_IntTriggerA6 59
V Start2_IntTriggerA7 60
#-------------------------------------------------------------------------------
# Enumerated type DI_StartConvertSelMux_t
#-------------------------------------------------------------------------------
E DI_StartConvertSelMux_t
V SampleClk_Internal 0
V SampleClk_PFI0 1
V SampleClk_PFI1 2
V SampleClk_PFI2 3
V SampleClk_PFI3 4
V SampleClk_PFI4 5
V SampleClk_PFI5 6
V SampleClk_PFI6 7
V SampleClk_PFI7 8
V SampleClk_PFI8 9
V SampleClk_PFI9 10
V SampleClk_RTSI0 11
V SampleClk_RTSI1 12
V SampleClk_RTSI2 13
V SampleClk_RTSI3 14
V SampleClk_RTSI4 15
V SampleClk_RTSI5 16
V SampleClk_RTSI6 17
V SampleClk_DIO_ChgDetect 18
V SampleClk_G0_Out 19
V SampleClk_Star_Trigger 20
V SampleClk_PFI10 21
V SampleClk_PFI11 22
V SampleClk_PFI12 23
V SampleClk_PFI13 24
V SampleClk_PFI14 25
V SampleClk_PFI15 26
V SampleClk_RTSI7 27
V SampleClk_G1_Out 28
V SampleClk_AI_Start 29
V SampleClk_Atrig 30
V SampleClk_Low 31
V SampleClk_PXIe_DStarA 32
V SampleClk_PXIe_DStarB 33
V SampleClk_G2_Out 34
V SampleClk_G3_Out 35
V SampleClk_G0_SampleClk 36
V SampleClk_G1_SampleClk 37
V SampleClk_G2_SampleClk 38
V SampleClk_G3_SampleClk 39
V SampleClk_AI_Convert 40
V SampleClk_AO_Update 43
V SampleClk_DO_Update 44
V SampleClk_IntTriggerA0 53
V SampleClk_IntTriggerA1 54
V SampleClk_IntTriggerA2 55
V SampleClk_IntTriggerA3 56
V SampleClk_IntTriggerA4 57
V SampleClk_IntTriggerA5 58
V SampleClk_IntTriggerA6 59
V SampleClk_IntTriggerA7 60
V SampleClk_FreqOut 61
#===============================================================================
# Register Group ChangeDetect
#===============================================================================
#-------------------------------------------------------------------------------
# DI_ChangeDetectStatusRegister Register Definition
R DI_ChangeDetectStatusRegister 32 0x10 Readable
F DI_ChangeDetectStatus 1
@ This bit reflects the state of the Change Detect Circuit. When
@ the bit is on, it means that the change detect circuit has
@ detected one of the registered events. Clear this bit with
@ the ChangeDetectIRQ_Acknowledge bitfield.
F DI_ChangeDetectError 1
@ This bit reflects the state of the Change Detect Error Circuit.
@ When the bit is on, it means that the change detect circuit
@ has issued two consecutive events without an acknowledge
@ from software (with the ChangeDetectIRQ_Acknowledge). Clear
@ this bit with the ChangeDetectErrorIRQ_Acknowledge bitfield.
F Reserved 30
#-------------------------------------------------------------------------------
# DI_ChangeIrqRE_Register Register Definition
R DI_ChangeIrqRE_Register 32 0x10 Writable --no-hardware-reset false
F DI_ChangeIrqRE 32
@ Set to check for rising edges on corresponding DI line.
#-------------------------------------------------------------------------------
# DI_ChangeDetectLatchedDI_Register Register Definition
R DI_ChangeDetectLatchedDI_Register 32 0x14 Readable
F DI_ChangeDetectLatchedDI 32
@ This register reflects the state of the DI lines at the time
@ the last masked change was detected including the change that
@ caused it. Software should mask lines not being used for static
@ digital input.
NOTE: This register is written
@ at all the events detected by the change detect circuit.
@ SW must check the Change Detect Error bit to make sure the
@ data being read is valid and coherent (for the case of reading
@ DI and PFI registers).
#-------------------------------------------------------------------------------
# DI_ChangeIrqFE_Register Register Definition
R DI_ChangeIrqFE_Register 32 0x14 Writable --no-hardware-reset false
F DI_ChangeIrqFE 32
@ Set to check for falling edges on corresponding DI line.
#-------------------------------------------------------------------------------
# DI_ChangeDetectLatchedPFI_Register Register Definition
R DI_ChangeDetectLatchedPFI_Register 16 0x18 Readable
F DI_ChangeDetectLatchedPFI 16
@ This register reflects the state of the PFI lines at the time
@ the last masked change was detected including the change that
@ caused it. Software should mask lines not being used for
@ static digital input.
NOTE: This register is written
@ at all the events detected by the change detect circuit.
@ SW must check the Change Detect Error bit to make sure the
@ data being read is valid and coherent (for the case of reading
@ DI and PFI registers).
#-------------------------------------------------------------------------------
# PFI_ChangeIrq_Register Register Definition
R PFI_ChangeIrq_Register 32 0x18 Writable --no-hardware-reset false
F PFI_ChangeIrqRE 16
@ Set to check for rising edges on corresponding PFI line.
F PFI_ChangeIrqFE 16
@ Set to check for falling edges on corresponding PFI line.
#-------------------------------------------------------------------------------
# DI_ChangeDetectIRQ_Register Register Definition
R DI_ChangeDetectIRQ_Register 32 0x24 Writable --no-soft-copy true
F ChangeDetectIRQ_Acknowledge 1 Strobe
@ Acknowledges the Change Detect Interrupt and clears the status
@ bit.
F ChangeDetectErrorIRQ_Acknowledge 1 Strobe
@ Acknowledges the Change Detect Error Interrupt and clears the
@ status bit.
F Reserved 2
F ChangeDetectIRQ_Disable 1 Strobe
@ Disables the Change Detect Interrupt.
F ChangeDetectIRQ_Enable 1 Strobe
@ Enables the Change Detect Interrupt. This interrupt fires any
@ time the change detect circuit detects one of the registered
@ events.
F ChangeDetectErrorIRQ_Disable 1 Strobe
@ Disables the Change detect Interrupt.
F ChangeDetectErrorIRQ_Enable 1 Strobe
@ Enables the Change Detect Error Interrupt. This interrupt fires
@ when two Change Detect Interrupts are generated without an
@ acknowledge from SW.
F Reserved 24
#===============================================================================
# Register Group DI
#===============================================================================
#-------------------------------------------------------------------------------
# DI_DMA_Select_Register Register Definition
R DI_DMA_Select_Register 8 0x00 Writable
F Reserved 4
F Reserved 3
F DI_DoneNotificationEnable 1
@ This bit enables the generation of the done notification on the
@ input stream. This notification happens after the last point
@ is written after a LastSC_TC event. After this notification
@ happens, no more data can be written until a FIFO reset
@ happens.
#-------------------------------------------------------------------------------
# Static_Digital_Input_Register Register Definition
R Static_Digital_Input_Register 32 0x0 Readable
F DI_StaticValue 32
@ This register reflects the state of the DI lines. Software should
@ mask lines not being used for static digital input.
#-------------------------------------------------------------------------------
# DI_FIFO_St_Register Register Definition
R DI_FIFO_St_Register 32 0x04 Readable
F CDI_FIFO_FullCount 16
@ Indicates the number of samples available to read in the CDI
@ FIFO.
F Reserved 16
#-------------------------------------------------------------------------------
# DI_Mode_Register Register Definition
R DI_Mode_Register 32 0x04 Writable
F Reserved 11
F DI_DigitalFiltersMode 1 . nDI::tDI_FilterMode_t
@ If in correlated mode, the filters will keep the output correlated
@ as long as the skew in the input lines is less than the
@ filter setting and the valid input lines remain stable for
@ two times the filter setting before changing again. If disabled,
@ the digital filters in DI will behave like the 6509 (input
@ lines need to be stable for twice the filter setting for
@ the change to be guaranteed in the output, this will have
@ better latency and jitter specs but will not guarantee correlation
@ between lines)
F DI_Data_Lane 2 . nDI::tDI_Data_Lane_t
@ Use to determine which byte or word lanes to read data from.
@ When the DI_DataWidth bitfield is 16 bits If 0, then
@ CDIO_15_0. If 1, then CDIO_31_16.
@ When the DI_DataWidth bitfield is 8 bits If 0, then
@ CDIO_7_0. If 1, then CDIO_15_8. If 2,
@ then CDIO_23_16. If 3, then CDIO_31_24.
F DI_DataWidth 2 . nDI::tDI_DataWidth_t
@ Use to determine the width of the data to be saved to the FIFO.
@ When the FIFO width is programmable, the FIFO width will
@ change with this bitfield . If the FIFO is of a set width, this
@ bitfield in combination with CDI_Data_Lane will determine
@ how the data is smeared across the FIFO data lines. If 0,
@ then data saved is 8-bits. If 1, then 16-bits. If 2 or more,
@ then 32-bits.
@
NOTE: The FIFO must be reset when this bitfield
@ is changed.
F Reserved 16
#-------------------------------------------------------------------------------
# DI_FIFO_Data_Register Register Definition
R DI_FIFO_Data_Register 32 0x08 Readable
F CDI_FIFO_Data 32
@ This register is used to read data from the DI FIFO 32 bits at
@ a time. This register should be used any time that DI_DataWidth
@ is set to 32 bits.
#-------------------------------------------------------------------------------
# DI_FIFO_Data_Register16 Register Definition
R DI_FIFO_Data_Register16 16 0x08 Readable
F CDI_FIFO_Data16 16
@ This register is used to read data from the DI FIFO 16 bits at
@ a time. This register should be used any time that DI_DataWidth
@ is set to 16 bits.
#-------------------------------------------------------------------------------
# DI_FIFO_Data_Register8 Register Definition
R DI_FIFO_Data_Register8 8 0x08 Readable
F CDI_FIFO_Data8 8
@ This register is used to read data from the DI FIFO 8 bits at
@ a time. This register should be used any time that DI_DataWidth
@ is set to 8 bits.
#-------------------------------------------------------------------------------
# DI_Mask_Enable_Register Register Definition
R DI_Mask_Enable_Register 32 0x08 Writable
F CDI_Mask 32 . nDI::tDI_Mask_t
@ Sets on a per bit basis whether the data will be written to the
@ FIFO, or the bit will be masked and a zero will be written
@ to the FIFO
#-------------------------------------------------------------------------------
# DI_Trigger_Select_Register Register Definition
R DI_Trigger_Select_Register 32 0x0C Writable
F DI_START1_Select 6 . nDI::tDI_START1_Select_t
@ This bitfield selects the DI_START1 trigger
F DI_START1_Edge 1
@ This bit enables edge-sensitive detection of the DI_START1 trigger:
@ Value 0 means Disabled (level-sensitive trigger)
@ Value 1 means Enabled (edge-sensitive trigger)
@ NOTE: Set this bit to 0 if DI_START1_Select
@ is set to 0 (DI_START1_Pulse).
F DI_START1_Polarity 1 . nDI::tDI_Polarity_t
@ This bit determines the polarity of the DI_START1 trigger NOTE:
@ Set this bit to 0 if DI_START1_Select is set to 0
@ (DI_START1_Pulse).
F DI_START2_Select 6 . nDI::tDI_START2_Select_t
@ This bitfield selects the DI_START2 trigger
F DI_START2_Edge 1
@ This bit enables edge detection of the DI_START2 trigger:
@ NOTE: Set this bit to 0 if DI_START2_Select is set to
@ 0 (DI_START2_Pulse).
F DI_START2_Polarity 1 . nDI::tDI_Polarity_t
@ This bit determines the polarity of DI_START2 trigger NOTE:
@ Set this bit to 0 if DI_START2_Select is set to 0 (DI_START2_Pulse).
F DI_External_Gate_Select 6 . nDI::tDI_External_Gate_Select_t
@ This bitfield enables and selects the external gate. You can
@ use the external gate to pause a digital input operation in
@ progress.
F Reserved 1
F DI_External_Gate_Polarity 1 . nDI::tDI_Polarity_t
@ This bit selects the polarity of the external gate signal
F DI_CONVERT_Source_Select 6 . nDI::tDI_StartConvertSelMux_t
@ Selects the DI_CONVERT source.
When you set this bitfield
@ to 0, the DI Timer is in internal DI_CONVERT mode. When you
@ select any other signal as the DI_CONVERT source, the DI Timer
@ is in external DI_CONVERT mode.
F Reserved 1
F DI_CONVERT_Source_Polarity 1 . nDI::tDI_Polarity_t
@ This bit selects the active edge of the DI_CONVERT source signal
#-------------------------------------------------------------------------------
# DI_FilterRegisterLo Register Definition
R DI_FilterRegisterLo 32 0x1C Writable
F DI0_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 0 Filter Selection.
F DI1_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 1 Filter Selection.
F DI2_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 2 Filter Selection.
F DI3_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 3 Filter Selection.
F DI4_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 4 Filter Selection.
F DI5_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 5 Filter Selection.
F DI6_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 6 Filter Selection.
F DI7_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 7 Filter Selection.
F DI8_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 8 Filter Selection.
F DI9_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 9 Filter Selection.
F DI10_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 10 Filter Selection.
F DI11_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 11 Filter Selection.
F DI12_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 12 Filter Selection.
F DI13_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 13 Filter Selection.
F DI14_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 14 Filter Selection.
F DI15_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 15 Filter Selection.
#-------------------------------------------------------------------------------
# DI_FilterRegisterHi Register Definition
R DI_FilterRegisterHi 32 0x20 Writable
F DI16_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 16 Filter Selection.
F DI17_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 17 Filter Selection.
F DI18_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 18 Filter Selection.
F DI19_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 19 Filter Selection.
F DI20_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 20 Filter Selection.
F DI21_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 21 Filter Selection.
F DI22_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 22 Filter Selection.
F DI23_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 23 Filter Selection.
F DI24_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 24 Filter Selection.
F DI25_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 25 Filter Selection.
F DI26_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 26 Filter Selection.
F DI27_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 27 Filter Selection.
F DI28_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 28 Filter Selection.
F DI29_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 29 Filter Selection.
F DI30_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 30 Filter Selection.
F DI31_Filter_Select 2 . nDI::tDI_Filter_Select_t
@ DI line 31 Filter Selection.