#****************************************************************************** # Counter.rbm # # (c) Copyright 2011 # National Instruments Corporation. # All rights reserved. # License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT # Refer to "MHDDK License Agreement.pdf" in the root of this distribution. # # Description: # rbm file for Counter. # This file is autogenerated. Do not modify it directly. # # All lines starting with # or C are comments # All lines starting with T define a register Type # All lines starting with TR define register name, type, offset # All lines starting with F are Fields within the preceding register, # Its name, size, attribute (Strobe|.) and type are defined. # #****************************************************************************** # Declaring RBM as a containable chip object. # This means all instances must specify an offset for it. --containable --generate-include "tCounterValues.h" #=============================================================================== # Register Group Enumerated_Types #=============================================================================== #------------------------------------------------------------------------------- # Enumerated type Gi_A_Select_t #------------------------------------------------------------------------------- E Gi_A_Select_t V A_PFI0 1 V A_PFI1 2 V A_PFI2 3 V A_PFI3 4 V A_PFI4 5 V A_PFI5 6 V A_PFI6 7 V A_PFI7 8 V A_PFI8 9 V A_PFI9 10 V A_RTSI0 11 V A_RTSI1 12 V A_RTSI2 13 V A_RTSI3 14 V A_RTSI4 15 V A_RTSI5 16 V A_RTSI6 17 V A_PXIe_DStarA 18 V A_PXIe_DStarB 19 V A_Star_Trig 20 V A_PFI10 21 V A_PFI11 22 V A_PFI12 23 V A_PFI13 24 V A_PFI14 25 V A_PFI15 26 V A_RTSI7 27 V A_Analog_trig 30 V A_LogicLow 31 V A_IntTrigA_0 46 V A_IntTrigA_1 47 V A_IntTrigA_2 48 V A_IntTrigA_3 49 V A_IntTrigA_4 50 V A_IntTrigA_5 51 V A_IntTrigA_6 52 V A_IntTrigA_7 53 #------------------------------------------------------------------------------- # Enumerated type Gi_Armed_St_t #------------------------------------------------------------------------------- E Gi_Armed_St_t V Not_Armed 0 V Armed 1 #------------------------------------------------------------------------------- # Enumerated type Gi_AuxCtrMode_t #------------------------------------------------------------------------------- E Gi_AuxCtrMode_t V Aux_Disabled 0 V Aux_FrequencyMeasurement 1 V Aux_FinitePulseTrain 2 V Aux_MinFinitePulseTrain 3 V Aux_GateEventCounting 4 V Aux_FinitePwmGeneration 5 #------------------------------------------------------------------------------- # Enumerated type Gi_B_Select_t #------------------------------------------------------------------------------- E Gi_B_Select_t V B_LogicLow0 0 V B_PFI0 1 V B_PFI1 2 V B_PFI2 3 V B_PFI3 4 V B_PFI4 5 V B_PFI5 6 V B_PFI6 7 V B_PFI7 8 V B_PFI8 9 V B_PFI9 10 V B_RTSI0 11 V B_RTSI1 12 V B_RTSI2 13 V B_RTSI3 14 V B_RTSI4 15 V B_RTSI5 16 V B_RTSI6 17 V B_PXIe_DStarA 18 V B_PXIe_DStarB 19 V B_Star_Trig 20 V B_PFI10 21 V B_PFI11 22 V B_PFI12 23 V B_PFI13 24 V B_PFI14 25 V B_PFI15 26 V B_RTSI7 27 V B_Analog_Trig 30 V B_LogicLow 31 V B_IntTrigA_0 46 V B_IntTrigA_1 47 V B_IntTrigA_2 48 V B_IntTrigA_3 49 V B_IntTrigA_4 50 V B_IntTrigA_5 51 V B_IntTrigA_6 52 V B_IntTrigA_7 53 #------------------------------------------------------------------------------- # Enumerated type Gi_Bank_Switch_Enable_t #------------------------------------------------------------------------------- E Gi_Bank_Switch_Enable_t V Disabled_If_Armed_Else_Write_To_X 0 V Enabled_If_Armed_Else_Write_To_Y 1 #------------------------------------------------------------------------------- # Enumerated type Gi_Load_Source_Select_t #------------------------------------------------------------------------------- E Gi_Load_Source_Select_t V Load_From_Register_A 0 V Load_From_Register_B 1 #------------------------------------------------------------------------------- # Enumerated type Gi_Bank_Switch_Mode_t #------------------------------------------------------------------------------- E Gi_Bank_Switch_Mode_t V Gate 0 V Software 1 V SampleClk 2 #------------------------------------------------------------------------------- # Enumerated type Gi_CountingMode_t #------------------------------------------------------------------------------- E Gi_CountingMode_t V NormalCounting 0 V QuadEncoderX1 1 V QuadEncoderX2 2 V QuadEncoderX4 3 V TwoPulseEncoder 4 V FrequencyMeasure 6 V FinitePulseTrain 7 #------------------------------------------------------------------------------- # Enumerated type Gi_Counting_Once_t #------------------------------------------------------------------------------- E Gi_Counting_Once_t V NoHardwareDisarm 0 V DisarmAtTcThatStops 1 V DisarmAtGateThatStops 2 V DisarmAtTcOrGateThatStops 3 #------------------------------------------------------------------------------- # Enumerated type Gi_Disabled_Enabled_t #------------------------------------------------------------------------------- E Gi_Disabled_Enabled_t V Disabled 0 V Enabled 1 #------------------------------------------------------------------------------- # Enumerated type Gi_Gate_Select_t #------------------------------------------------------------------------------- E Gi_Gate_Select_t V Gate_DioChgDetect 0 V Gate_PFI0 1 V Gate_PFI1 2 V Gate_PFI2 3 V Gate_PFI3 4 V Gate_PFI4 5 V Gate_PFI5 6 V Gate_PFI6 7 V Gate_PFI7 8 V Gate_PFI8 9 V Gate_PFI9 10 V Gate_RTSI0 11 V Gate_RTSI1 12 V Gate_RTSI2 13 V Gate_RTSI3 14 V Gate_RTSI4 15 V Gate_RTSI5 16 V Gate_RTSI6 17 V Gate_AI_START2 18 V Gate_StarTrig 19 V Gate_G_PairedOut 20 V Gate_PFI10 21 V Gate_PFI11 22 V Gate_PFI12 23 V Gate_PFI13 24 V Gate_PFI14 25 V Gate_PFI15 26 V Gate_RTSI7 27 V Gate_AI_START1 28 V Gate_G_PairedSrc 29 V Gate_Atrig 30 V Gate_PXIe_DStarA 31 V Gate_PXIe_DStarB 32 V Gate_IntTrigA_0 41 V Gate_IntTrigA_1 42 V Gate_IntTrigA_2 43 V Gate_IntTrigA_3 44 V Gate_IntTrigA_4 45 V Gate_IntTrigA_5 46 V Gate_IntTrigA_6 47 V Gate_IntTrigA_7 48 V Gate_DI_START1 59 V Gate_DI_START2 60 V Gate_AO_START1 61 V Gate_DO_START1 62 V Gate_LogicLow 63 #------------------------------------------------------------------------------- # Enumerated type Gi_GatingMode_t #------------------------------------------------------------------------------- E Gi_GatingMode_t V GateDisabled 0 V LevelGating 1 V AssertingEdgeGating 2 V DeassertingEdgeGating 3 #------------------------------------------------------------------------------- # Enumerated type Gi_HW_Arm_Select_t #------------------------------------------------------------------------------- E Gi_HW_Arm_Select_t V HwArm_DIO_ChgDetect 0 V HwArm_PFI0 1 V HwArm_PFI1 2 V HwArm_PFI2 3 V HwArm_PFI3 4 V HwArm_PFI4 5 V HwArm_PFI5 6 V HwArm_PFI6 7 V HwArm_PFI7 8 V HwArm_PFI8 9 V HwArm_PFI9 10 V HwArm_RTSI0 11 V HwArm_RTSI1 12 V HwArm_RTSI2 13 V HwArm_RTSI3 14 V HwArm_RTSI4 15 V HwArm_RTSI5 16 V HwArm_RTSI6 17 V HwArm_AI_START2 18 V HwArm_Star_Trig 19 V HwArm_G_PairedOut 20 V HwArm_PFI10 21 V HwArm_PFI11 22 V HwArm_PFI12 23 V HwArm_PFI13 24 V HwArm_PFI14 25 V HwArm_PFI15 26 V HwArm_RTSI7 27 V HwArm_AI_START1 28 V HwArm_Analog_Trig 29 V HwArm_DI_Start1 30 V HwArm_AO_Start1 31 V HwArm_DO_Start1 32 V HwArm_PXIe_DStarA 33 V HwArm_PXIe_DStarB 34 V HwArm_IntTrigA_0 48 V HwArm_IntTrigA_1 49 V HwArm_IntTrigA_2 50 V HwArm_IntTrigA_3 51 V HwArm_IntTrigA_4 52 V HwArm_IntTrigA_5 53 V HwArm_IntTrigA_6 54 V HwArm_IntTrigA_7 55 #------------------------------------------------------------------------------- # Enumerated type Gi_HwArmSyncMode_t #------------------------------------------------------------------------------- E Gi_HwArmSyncMode_t V SyncDefault 0 V SyncSlave 1 V SyncMaster 2 #------------------------------------------------------------------------------- # Enumerated type Gi_Index_Mode_t #------------------------------------------------------------------------------- E Gi_Index_Mode_t V IndexModeCleared 0 V IndexModeSet 1 #------------------------------------------------------------------------------- # Enumerated type Gi_Index_Phase_t #------------------------------------------------------------------------------- E Gi_Index_Phase_t V A_low_B_low 0 V A_low_B_high 1 V A_high_B_low 2 V A_high_B_high 3 #------------------------------------------------------------------------------- # Enumerated type Gi_Loading_On_Gate_t #------------------------------------------------------------------------------- E Gi_Loading_On_Gate_t V NoCounterReloadOnGate 0 V ReloadOnStopGate 1 #------------------------------------------------------------------------------- # Enumerated type Gi_Loading_On_TC_t #------------------------------------------------------------------------------- E Gi_Loading_On_TC_t V RolloverOnTC 0 V ReloadOnTC 1 #------------------------------------------------------------------------------- # Enumerated type Gi_Output_Mode_t #------------------------------------------------------------------------------- E Gi_Output_Mode_t V TC_mode 1 V Toggle_Output_On_TC 2 V Toggle_Output_On_TC_or_Gate 3 #------------------------------------------------------------------------------- # Enumerated type Gi_Output_St_t #------------------------------------------------------------------------------- E Gi_Output_St_t V Low 0 V High 1 #------------------------------------------------------------------------------- # Enumerated type Gi_Polarity_t #------------------------------------------------------------------------------- E Gi_Polarity_t V ActiveHigh 0 V ActiveLow 1 #------------------------------------------------------------------------------- # Enumerated type Gi_Reload_Source_Switching_t #------------------------------------------------------------------------------- E Gi_Reload_Source_Switching_t V UseSameLoadRegister 0 V UseAlternatingLoadRegisters 1 #------------------------------------------------------------------------------- # Enumerated type Gi_SampleClkSampleMode_t #------------------------------------------------------------------------------- E Gi_SampleClkSampleMode_t V SC_NextSaved 0 V SC_LastSaved 1 #------------------------------------------------------------------------------- # Enumerated type Gi_SampleClockMode_t #------------------------------------------------------------------------------- E Gi_SampleClockMode_t V SC_Disabled 0 V SC_SingleSample 1 V SC_DoubleSampleRF 2 V SC_DoubleSampleFR 3 V SC_MainAndAux 4 #------------------------------------------------------------------------------- # Enumerated type Gi_SampleClockSelect_t #------------------------------------------------------------------------------- E Gi_SampleClockSelect_t V SampleClk_SwPulse 0 V SampleClk_PFI0 1 V SampleClk_PFI1 2 V SampleClk_PFI2 3 V SampleClk_PFI3 4 V SampleClk_PFI4 5 V SampleClk_PFI5 6 V SampleClk_PFI6 7 V SampleClk_PFI7 8 V SampleClk_PFI8 9 V SampleClk_PFI9 10 V SampleClk_RTSI0 11 V SampleClk_RTSI1 12 V SampleClk_RTSI2 13 V SampleClk_RTSI3 14 V SampleClk_RTSI4 15 V SampleClk_RTSI5 16 V SampleClk_RTSI6 17 V SampleClk_Star_Trig 19 V SampleClk_DIO_ChgDetect 20 V SampleClk_PFI10 21 V SampleClk_PFI11 22 V SampleClk_PFI12 23 V SampleClk_PFI13 24 V SampleClk_PFI14 25 V SampleClk_PFI15 26 V SampleClk_RTSI7 27 V SampleClk_AI_START 28 V SampleClk_Atrig 30 V SampleClk_DI_Convert 31 V SampleClk_DI_Start1 32 V SampleClk_AI_Convert 33 V SampleClk_AI_Start1 34 V SampleClk_AI_Start2 35 V SampleClk_AO_Update 36 V SampleClk_DO_Update 37 V SampleClk_PXIe_DStarA 38 V SampleClk_PXIe_DStarB 39 V SampleClk_IntTrigA_0 48 V SampleClk_IntTrigA_1 49 V SampleClk_IntTrigA_2 50 V SampleClk_IntTrigA_3 51 V SampleClk_IntTrigA_4 52 V SampleClk_IntTrigA_5 53 V SampleClk_IntTrigA_6 54 V SampleClk_IntTrigA_7 55 #------------------------------------------------------------------------------- # Enumerated type Gi_Second_Gate_Mode_t #------------------------------------------------------------------------------- E Gi_Second_Gate_Mode_t V DisabledSecondGate 0 V SecondGateAssertFirstDeassertsGate 1 #------------------------------------------------------------------------------- # Enumerated type Gi_Second_Gate_Select_t #------------------------------------------------------------------------------- E Gi_Second_Gate_Select_t V Gate2_LogicLow 0 V Gate2_PFI0 1 V Gate2_PFI1 2 V Gate2_PFI2 3 V Gate2_PFI3 4 V Gate2_PFI4 5 V Gate2_PFI5 6 V Gate2_PFI6 7 V Gate2_PFI7 8 V Gate2_PFI8 9 V Gate2_PFI9 10 V Gate2_RTSI0 11 V Gate2_RTSI1 12 V Gate2_RTSI2 13 V Gate2_RTSI3 14 V Gate2_RTSI4 15 V Gate2_RTSI5 16 V Gate2_RTSI6 17 V Gate2_AI_START1 18 V Gate2_Star_Trig 19 V Gate2_G_PairedOut 20 V Gate2_PFI10 21 V Gate2_PFI11 22 V Gate2_PFI12 23 V Gate2_PFI13 24 V Gate2_PFI14 25 V Gate2_PFI15 26 V Gate2_RTSI7 27 V Gate2_G_PairedGate 28 V Gate2_G_PairedSrc 29 V Gate2_G_Gate1 30 V Gate2_PXIe_DStarA 31 V Gate2_PXIe_DStarB 32 V Gate2_Atrig 33 V Gate2_DioChgDetect 34 V Gate2_AI_START2 35 V Gate2_IntTrigA_0 46 V Gate2_IntTrigA_1 47 V Gate2_IntTrigA_2 48 V Gate2_IntTrigA_3 49 V Gate2_IntTrigA_4 50 V Gate2_IntTrigA_5 51 V Gate2_IntTrigA_6 52 V Gate2_IntTrigA_7 53 #------------------------------------------------------------------------------- # Enumerated type Gi_Source_Select_t #------------------------------------------------------------------------------- E Gi_Source_Select_t V Src_PFI0 1 V Src_PFI1 2 V Src_PFI2 3 V Src_PFI3 4 V Src_PFI4 5 V Src_PFI5 6 V Src_PFI6 7 V Src_PFI7 8 V Src_PFI8 9 V Src_PFI9 10 V Src_RTSI0 11 V Src_RTSI1 12 V Src_RTSI2 13 V Src_RTSI3 14 V Src_RTSI4 15 V Src_RTSI5 16 V Src_RTSI6 17 V Src_TB2 18 V Src_G_PairedTC 19 V Src_G_PairedGate 20 V Src_PFI10 21 V Src_PFI11 22 V Src_PFI12 23 V Src_PFI13 24 V Src_PFI14 25 V Src_PFI15 26 V Src_RTSI7 27 V Src_TB1 28 V Src_PXIClk10 29 V Src_TB3 30 V Src_StarTrig 32 V Src_PXIe_DStarA 33 V Src_PXIe_DStarB 34 V Src_IntTrigA_0 43 V Src_IntTrigA_1 44 V Src_IntTrigA_2 45 V Src_IntTrigA_3 46 V Src_IntTrigA_4 47 V Src_IntTrigA_5 48 V Src_IntTrigA_6 49 V Src_IntTrigA_7 50 V Src_DIO_ChgDetect 59 V Src_Atrig 60 #------------------------------------------------------------------------------- # Enumerated type Gi_Stop_Mode_t #------------------------------------------------------------------------------- E Gi_Stop_Mode_t V StopOnGateCondition 0 V StopAtGateOrFirstTC 1 V StopAtGateOrSecondTC 2 #------------------------------------------------------------------------------- # Enumerated type Gi_Trigger_Mode_For_Edge_Gate_t #------------------------------------------------------------------------------- E Gi_Trigger_Mode_For_Edge_Gate_t V FirstGateStartSecondGateStops 0 V FirstGateStopsSecondGateStarts 1 V GateEdgeStarts 2 V GateLoads 3 #------------------------------------------------------------------------------- # Enumerated type Gi_Up_Down_t #------------------------------------------------------------------------------- E Gi_Up_Down_t V CountDown 0 V CountUp 1 V Gi_B_High_Up 2 V Gi_Gate_Active_Up 3 #------------------------------------------------------------------------------- # Enumerated type Gi_Z_Select_t #------------------------------------------------------------------------------- E Gi_Z_Select_t V Z_PFI0 1 V Z_PFI1 2 V Z_PFI2 3 V Z_PFI3 4 V Z_PFI4 5 V Z_PFI5 6 V Z_PFI6 7 V Z_PFI7 8 V Z_PFI8 9 V Z_PFI9 10 V Z_RTSI0 11 V Z_RTSI1 12 V Z_RTSI2 13 V Z_RTSI3 14 V Z_RTSI4 15 V Z_RTSI5 16 V Z_RTSI6 17 V Z_PXIe_DStarA 18 V Z_PXIe_DStarB 19 V Z_Star_Trig 20 V Z_PFI10 21 V Z_PFI11 22 V Z_PFI12 23 V Z_PFI13 24 V Z_PFI14 25 V Z_PFI15 26 V Z_RTSI7 27 V Z_Analog_Trig 30 V Z_LogicLow 31 V Z_IntTrigA_0 46 V Z_IntTrigA_1 47 V Z_IntTrigA_2 48 V Z_IntTrigA_3 49 V Z_IntTrigA_4 50 V Z_IntTrigA_5 51 V Z_IntTrigA_6 52 V Z_IntTrigA_7 53 #=============================================================================== # Register Group TIO #=============================================================================== #------------------------------------------------------------------------------- # Gi_Command_Register Register Definition R Gi_Command_Register 16 0x0 Writable --no-hardware-reset false F Gi_Arm 1 Strobe @ Setting this bit to 1 arms the general-purpose counter. The counter @ remains armed (and Gi_Armed_St will remain set) until @ it is disarmed, either by hardware or by setting Gi_Disarm @ to 1. F Reserved 1 F Gi_Load 1 Strobe @ Setting this bit to 1 loads the contents of the selected load @ register into the general-purpose counter. This bit should @ only be set when the counter is disarmed. It will be ignored @ otherwise. This bit is cleared automatically. F Reserved 1 F Gi_Disarm 1 Strobe @

Setting this bit to 1 disarms the general-purpose counter. @ This bit is cleared automatically.

The counter has @ three basic modes of operation:

F Reserved 2 F Gi_WrLoadRegsFromFifo 1 Strobe @ This bit forces a write to the selected bank of load registers @ from the FIFO. This bit only works when the Output FIFO is @ enabled and the counter is not armed. Use this bit to Write @ Bank X and Y from the FIFO before arming. The counter will @ still need to be preloaded. The Gi_ForcedWrFromFifoInProgSt @ bit will set when this command is received and will clear once @ the operation is completed. F Reserved 1 F Gi_Bank_Switch_Start 1 Strobe @ Setting this bit to 1 indicates load register bank switching @ on the condition selected by Gi_Bank_Switch_Mode. You can use @ this bit in an interrupt service program. This bit is cleared @ automatically. F Reserved 3 F Gi_Arm_Paired_Counter 1 Strobe @ Setting this bit to 1 arms this counter's pair. For example, @ setting Gi_Arm_Paired_Counter of counter 1 will arm counter @ 0, and vice versa. The paired counter remains armed (and the @ bit remains set) until it is disarmed, either by hardware or @ by setting its Gi_Disarm to 1. F Gi_Reset 1 Strobe @ Setting this bit to 1 resets the counter, clears Gi_Arm and Gi_Arm_Copy, @ clears the Gi_Mode_Register, and clears the appropriate @ bits of the Gi_Input_Select_Register. This bit is cleared @ automatically. F Gi_Disarm_Paired_Counter 1 Strobe @ Setting this bit to 1 disarms this counter's pair. For example, @ setting Gi_Disarm_Paired_Counter of counter 0 disarms counter @ 1, and vice versa. This bit is cleared automatically. #------------------------------------------------------------------------------- # Gi_Mode_Register Register Definition R Gi_Mode_Register 16 0x2 Writable --no-hardware-reset false F Gi_Gating_Mode 2 . nCounter::tGi_GatingMode_t @ This bit enables and selects the counter gating mode. When Gi_Gating_Mode @ is GateDisabled, gate level is available only for @ control of counting direction (up/down), and for no other @ purpose. F Gi_Gate_On_Both_Edges 1 . nCounter::tGi_Disabled_Enabled_t @ This bit enables you to use both gate edges to generate the gate @ interrupt and/or to control counter operation.

NOTE @ This bit also affects where interrupts are generated. F Gi_Trigger_Mode_For_Edge_Gate 2 . nCounter::tGi_Trigger_Mode_For_Edge_Gate_t @

This bit selects the triggering mode, if gating is not disabled @

Selections FirstGateStartSecondGateStops and @ FirstGateStopsSecondGateStarts are valid only if Gi_Stop_Mode @ is set to StopOnGateCondition (no hardware limit on this). @ Selections FirstGateStartSecondGateStops, FirstGateStopsSecondGateStarts, @ and GateEdgeStarts are valid only if Gi_Gating_Mode @ is set to AssertingEdgeGating or DeassertingEdgeGating. @ Selection GateLoads is valid only if Gi_Gating_Mode @ is not set to GateDisabled.

F Gi_Stop_Mode 2 . nCounter::tGi_Stop_Mode_t @

This bit selects the condition on which the counter stops. @

Notice that, regardless of this bitfield setting, @ you can always use the software disarm command, Gi_Disarm, @ to stop the counter. The gate condition that stops the counter @ is determined by Gi_Gating_Mode (in case of level gating) @ or by a combination of Gi_Gating_Mode and Gi_Trigger_Mode_For_Edge_Gate @ (in case of edge gating). Selections StopAtGateOrFirstTC @ and StopAtGateOrSecondTC are valid only if Gi_Trigger_Mode_For_Edge_Gate @ is set to GateEdgeStarts (no hardware @ limitation, so if invalid the acquisition is invalid).

F Gi_Load_Source_Select 1 . nCounter::tGi_Load_Source_Select_t @ If the general-purpose counter is disarmed, this bit selects @ the initial counter load register:
  1. Load register @ A
  2. Load register B

NOTE @ The source for subsequent loads depends on Gi_Reload_Source_Switching. @ If the general-purpose counter is armed, writing @ to this bit has no effect. F Gi_Output_Mode 2 . nCounter::tGi_Output_Mode_t @

This bit selects the mode for the G_OUT signal.

NOTE:The @ Toggle modes (on TC or Gate) are not reset when @ disarmed . This is to allow the counter to keep the value of @ the output after the operation is complete. The logic involved @ in generating the toggle values is reset when the bitfield @ is set to TC. So when the STC3 is being configured to use @ one of the toggle bits, the Gi_Output_Mode bitfield should @ be set to TC; then the STC3 should be configured; and finally, @ the Gi_Output_Mode field set to the toggle mode of choice. @ This will prevent glitches on the output and will guarantee @ that the output will start at the right value.

F Gi_Counting_Once 2 . nCounter::tGi_Counting_Once_t @ This bit determines whether the hardware disarms the counter @ when the counter stops due to a hardware condition. F Gi_Loading_On_TC 1 . nCounter::tGi_Loading_On_TC_t @ This bit determines the counter behavior on TC:
    @
  1. Roll over on TC
  2. Reload on TC
F Gi_ForceSourceEqualToTimebase 1 @ When this bit is cleared, the counter operates with the TB3 signal @ (normally 100 MHz) as the main timebase of the counter. @ In the case of an external source, the counter samples the @ external source with the timebase, and then re-syncs the outputs. @ This works fine for frequencies up to the timebase frequency @ divided by 4 (25 MHz in the case of 100 MHz timebase). @ In case a higher source signal is needed, the counter can @ be set to use the external signal as the timebase. This is done @ by setting this bit. The counter assumes its timebase is @ a free running signal.

NOTE When this bit @ is set, the counter relies on the user provided source to operate. @ If that source is very slow or not present, then the @ counter may not respond to normal operations (such as disarm). @ See the documentation of the Disarm bit for more details @ on how to recover from this situation. F Gi_Loading_On_Gate 1 . nCounter::tGi_Loading_On_Gate_t @ This bit determines whether the gate signal causes counter reload: @

  1. Gate signal does not cause counter @ reload
  2. Counter is reloaded on gate edge that stops @ the counter, unless edge gating is used and Gi_Trigger_Mode_For_Edge_Gate @ is set to kGateLoads. In the later case, the counter @ is reloaded on every Selected Gate edge.

NOTE @ Reloading occurs on active source edge. F Gi_Reload_Source_Switching 1 . nCounter::tGi_Reload_Source_Switching_t @ If Gi_Gate_Select_Load_Source is set to 0, this bit enables load @ register selection in the following manner:

    @
  1. Always use the same load register
  2. Alternate @ between the two load registers
#------------------------------------------------------------------------------- # Gi_HW_Save_Register Register Definition R Gi_HW_Save_Register 32 0x4 Readable --no-hardware-reset false F Gi_HW_Save_Value 32 @ This register contains the last value of the counter saved by @ the gate or sample clock based on their configuration. This @ register should not be necessary now that the counters have @ a FIFO for input data. #------------------------------------------------------------------------------- # Gi_Load_A_Register Register Definition R Gi_Load_A_Register 32 0x4 Writable --no-hardware-reset false F Gi_Load_A 32 @ This bitfield is the load value A for the general- purpose counter. @ If load register A is the selected load register, the @ counter loads the value contained in this bitfield on Gi_Load, @ on the counter TC, and on the G_GATE induced counter reload @ condition (if G_GATE reloading is enabled). #------------------------------------------------------------------------------- # Gi_Load_B_Register Register Definition R Gi_Load_B_Register 32 0x8 Writable --no-hardware-reset false F Gi_Load_B 32 @ This bitfield is the load value B for the general- purpose counter. @ If load register B is the selected load register, the @ counter loads the value contained in this bitfield on Gi_Load, @ on the counter TC, and on the G_GATE induced counter reload @ condition (if G_GATE reloading is enabled). #------------------------------------------------------------------------------- # Gi_Save_Register Register Definition R Gi_Save_Register 32 0x8 Readable --no-hardware-reset false F Gi_Save_Value 32 @ This register allows a safe read of the current value of the @ counter. #------------------------------------------------------------------------------- # Gi_Input_Select_Register Register Definition R Gi_Input_Select_Register 16 0xC Writable --no-hardware-reset false F Gi_Gate_Polarity 1 . nCounter::tGi_Polarity_t @ This bit selects the polarity of the G_GATE input signal.
  1. Active high
  2. Active low
F Gi_Source_Select 6 . nCounter::tGi_Source_Select_t @ This bitfield selects the general-purpose counter source. F Gi_Gate_Select 6 . nCounter::tGi_Gate_Select_t @ This bitfield selects the G_GATE source for the general- purpose @ counter. F Gi_Gate_Select_Load_Source 1 . nCounter::tGi_Disabled_Enabled_t @ This bit enables the selection of the load register bank by the @ counter gate.

NOTE When this bit is set to 1, @ an active gate level selects load register bank X, and an inactive @ gate level selects load register bank Y. Also, Gi_Reload_Source_Switching @ is ignored. This feature can be used only @ in conjunction with level gating. F Gi_Output_Polarity 1 . nCounter::tGi_Polarity_t @ This bit selects the polarity of the G_OUT pulse (in the TC mode) @ or the initial G_OUT level (in the toggle output mode): @

  1. Active high pulse or initial low level
    2. @
  2. Active low pulse or initial high level
F Gi_Source_Polarity 1 . nCounter::tGi_Polarity_t @ This bit selects the active edge of the general-purpose counter @ source:
  1. Rising edge
  2. Falling edge
    3. @
#------------------------------------------------------------------------------- # Gi_Status_Register Register Definition R Gi_Status_Register 32 0xc Readable --no-hardware-reset false F Gi_Output_St 1 . nCounter::tGi_Output_St_t @ This bit indicates the current G_OUT state for the counter (after @ the polarity selection). F Reserved 1 F Gi_Counting_St 1 @ If the counter is armed, this bit indicates whether the counter @ is counting.

NOTE If the counter is not armed, @ this bit should be ignored. F Reserved 1 F Gi_Next_Load_Source_St 1 @ This bit indicates the next load source of the counter. F Reserved 3 F Gi_Armed_St 1 . nCounter::tGi_Armed_St_t @ This bit indicates whether the counter is armed. SW must poll @ on this bit after issuing arm/disarm commands until the command @ takes effect. F Reserved 1 F Gi_No_Load_Between_Gates_St 1 @ This bit indicates that a counter reload did not occur between @ two relevant G_GATE edges. F Gi_DRQ_Error 1 @ DMA Request Error - This bit is set when a DMA overflow error @ occurs on a read operation or when an underflow error occurs @ on a write operation. When reading, this bit sets if a save @ request occurs when the FIFO is full and another DMA read @ follows. The save request does not corrupt the data when the @ FIFO is received after completion.
When writing, an error @ is set if the bank switches to a new bank before the registers @ on that bank have been written. This is usually a FIFO @ underflow error. F Gi_TC_Error_St 1 @ This bit indicates the detection of a TC latency error.

NOTE @ A TC latency error is detected if Gi_TC_Interrupt_Ack @ is not set between two counter TCs. This allows you to @ detect large interrupt latencies and potential problems associated @ with them. To clear this bit, set Gi_TC_Error_Confirm @ to 1. F Reserved 1 F Gi_Gate_Error_St 1 @ This bit indicates the detection of a counter gate acknowledge @ latency error.

NOTE Gi_Gate_Error_St is set when @ a second gate interrupt occurs before the first gate interrupt @ is acknowledged. To clear this bit, set Gi_Gate_Error_Confirm. F Gi_DRQ_St 1 @ DMA Request Status - This bit is set when the counter needs DMA @ service and clears automatically when the request is serviced. F Gi_SampleClockOverrun_St 1 @ This bit indicates a Sample Clock overrun error. Clear this bit @ using the Gi_SampleClockOverrunErrorAck bit.

NOTE @ If the Gi_SampleClockStopOnError bit is set, the counter @ will stop acquiring data when the error occurs. F Gi_SampleClockInterruptSt 1 @ This bit indicates a Sample Clock Interrupt. This interrupt, @ when enabled, asserts with a valid sample clock that will result @ in writing new data to the FIFO: either a sample clock @ with no error, or a sample clock overrun when not in stop on @ error mode. Clear this bit using the Gi_SampleClockInterruptAck @ bit. F Gi_Bank_St 1 @ This bit indicates the load register bank used by the counter. F Reserved 1 F Gi_Gate_St 1 @ This bit indicates status of the general-purpose counter gate. @

NOTE This bit can only be used in the level-gating @ mode.

NOTE The state of this bit reflects the @ gate value after polarity compensation. F Reserved 2 F Gi_Gate_Interrupt_St 1 @ This bit indicates whether a gate interrupt has occurred.

NOTE @ This bit can be cleared by setting Gi_Gate_Interrupt_Ack @ to 1. F Gi_TC_St 1 @ This bit indicates whether the general-purpose counter has reached @ TC. This bit is cleared by setting Gi_TC_Interrupt_Ack @ to 1. F Gi_GateSwitchError_St 1 @ This bit indicates if a gate switch error happened in an output @ generation, i.e. a new gate comes requesting the counter @ to switch banks when the counter still has a switch pending @ from the previous gate. This reflects that the frequency of @ the output is less than the frequency of the gate. This bit @ clears with the Gi_GateSwitchError_Ack command bitfield and @ can generate an interrupt if enabled by Gi_GateSwitchErrorInt_En @ mode bit. F Gi_DisarmEventInterruptSt 1 @ This bit indicates a Disarm Event Interrupt. This interrupt, @ when enabled, asserts with a Disarm Event event is detected. @ Clear this bit using the Gi_Disarm_Interrupt_Ack bit. F Gi_ForcedWrFromFifoInProgSt 1 @ This bit indicates that a set of writes to the load registers @ initiated by writing to Gi_WrLoadRegsFromFifo is in progress. @ It is guaranteed by HW that if this bit is zero after writing @ the Gi_WrLoadRegsFromFifo bit, it means that the HW is @ done writing the load registers. F Gi_WritesTooFastErrorSt 1 @ A "Writes too fast error" happens when SW writes twice to the @ same bank before a switch event occurs. The event itself can @ be the switching of the banks by the counter (when Gi_WriteOnSwitchRequest @ =0) or can be the scheduling of the switch, @ as in a gate event (when Gi_WriteOnSwitchRequest =1).

@ It is possible to get an interrupt on this error. Clear @ the error and the status by writing one to Gi_WritesTooFastErrorAck. F Gi_AuxTC_ErrorEventSt 1 @ Aux Counter TC Error event Status. This event happens when a @ Aux TC event happens before the previous one has been acknowledged. F Gi_AuxTC_EventSt 1 @ Aux Counter TC event Status. This event can be useful for Finite @ dynamic pulse train generation, or to generate interrupts @ every number of pulse train generation waveform switches. F Reserved 1 #------------------------------------------------------------------------------- # Gi_Autoincrement_Register Register Definition R Gi_Autoincrement_Register 16 0xe Writable --no-hardware-reset false F Gi_Autoincrement 8 @ This 8-bit register holds a fixed value that is added to the @ contents of load register A after each counter reload, so that @ on the next reload the counter loads the incremented value. @ You should use the autoincrement feature in pulse-train generation @ for ETS to automatically increase the pulse delay @ after each trigger. F Reserved 8 #------------------------------------------------------------------------------- # Gi_Counting_Mode_Register Register Definition R Gi_Counting_Mode_Register 16 0x10 Writable F Gi_Counting_Mode 3 . nCounter::tGi_CountingMode_t @ This field determines the counting mode to use to interface to @ different encoders and applications. F Gi_HW_Arm_Polarity 1 . nCounter::tGi_Polarity_t @ This bit sets the polarity of the HW Arm signal. Writing a 1 @ to this bit sets the polarity to active low. 0 means active @ high. F Gi_Index_Mode 1 . nCounter::tGi_Index_Mode_t @ The effect of setting this bit depends on the counting mode. @ This bit can be written at run time when the counter is programmed @ for Quadrature or Two-Pulse mode to enable or disable @ Z index loading. For any other mode, it should be set before @ arming and remain constant. F Gi_Index_Phase 2 . nCounter::tGi_Index_Phase_t @ This bitfield determines the state of the A and B quadrature @ signals, and is where the index (or Z signal) is acted upon. @ The Z index can span multiple phases of the quadrature, but @ you should reload the counter in only one of the phases. F Gi_HW_Arm_Enable 1 @ Setting this bit enables the counter to be armed @ by a signal from the source specified by Gi_HW_Arm_Select. @ After configuring the HW_Arm settings, the Gi_Arm bit should @ be set. F Gi_HW_Arm_Select 6 . nCounter::tGi_HW_Arm_Select_t @ This bitfield selects the source for the HW arm signal. F Gi_Prescale 1 @ When this bit is enabled, a high-speed counter divides the selected @ source by eight (or two) before clocking the counter. @ In prescale mode, you can measure signal frequencies that exceed @ the 100 MHz limit of the counters. The division ratio @ is selectable using the Gi_Prescale_Div_2 bitfield. F Gi_Prescale_Div_2 1 @ When prescaling is enabled, set this bit to change the prescale @ value from 8 to 2.

  1. Division Ratio = 2
    2. @
  2. Division Ratio = 8
#------------------------------------------------------------------------------- # Gi_FifoStatusRegister Register Definition R Gi_FifoStatusRegister 32 0x10 Readable F Gi_FifoStatus 32 @ This bitfield indicates the FIFO full status of the input FIFO @ in units of samples. #------------------------------------------------------------------------------- # Gi_Second_Gate_Register Register Definition R Gi_Second_Gate_Register 16 0x12 Writable F Gi_Second_Gate_Mode 1 . nCounter::tGi_Second_Gate_Mode_t @

The second gate feature allows one signal to start the counter @ and another signal to stop the counter for two-edge separation @ measurements or for pulse-width measurements.

@

When 0, The Second Gate is disabled

When 1, The @ actual gate signal is modified with a combination of the first @ and second gate. An assertion of the second gate signals @ asserts the counter gate, and an assertion of the gate signal @ deasserts the gate. You can use this new gate signal for @ start and stop operations.

Gi_Second_Gate_Mode is also @ useful in pulse-width measurements. The level gating mode @ starts counting if the counter is armed while the gate is @ high, so the first measurement may be incorrect (too short). @ Using the selected gate input to the second gate and inverting @ both gate and second gate polarity forces a rising edge @ to occur before the gate asserts. As a result, the first pulse @ is measured.

Gi_Second_Gate_Mode is also used for @ two-edge separation measurements.

F Reserved 6 F Gi_Second_Gate_Select 6 . nCounter::tGi_Second_Gate_Select_t @ This field selects the signal used as the second gate for the @ counter. F Gi_Second_Gate_Polarity 1 . nCounter::tGi_Polarity_t @ Setting this bit inverts the selected second gate, changing the @ polarity. F Reserved 2 #------------------------------------------------------------------------------- # Gi_DMA_Config_Register Register Definition R Gi_DMA_Config_Register 16 0x14 Writable --initial-value 0x0000 F Gi_DMA_Enable 1 @ Direct Memory Access Enable - When this bit is set, an additional @ DMA mode is added for streaming counts into or out of the @ counters.
  • The read mode uses the @ counter FIFO to increase the rate at which pulse or period measurements @ are made. If a DMA channel (stream) is assigned @ to the counter, the data transfer will happen automatically. @ If the data transfer happens through PIO, then the FIFO can @ be read from the Gi_RdFifoRegister .
  • For @ pulse generation, the DMA can reload the load register when @ a bank switch occurs. DRQ asserts on the bank switch and @ clears when the last load register (register B) is written. @ When using PIO the data is written to the Gi_AutomaticLoadRegister, @ which automatically writes register A and then register @ B as it receives data. If using the FIFO (Gi_WrFifoEnable), @ the counter will load the data automatically from the FIFO. @ Data may be added to the FIFO either by PIO (write to Gi_WrFifoRegister), @ or via DMA when a DMA channel (stream) is @ assigned to the counter.
    • F Gi_DMA_Write 1 @ Direct Memory Access Write - This bit indicates the direction @ of the DMA operation. The counter FIFO must be reset with Gi_DMA_Reset @ when the value of this field changes. F Reserved 1 F Gi_DMA_Reset 1 Strobe @ Direct Memory Access Reset - Setting this bit resets the pointer @ used to track. This bit should be set as a part of initializing @ DMA. It is cleared automatically. Setting this bit also @ clears the active (as determined by DMA_Write) FIFO. After @ setting this bit, a read or bus flush should follow to ensure @ that the reset is complete before any direct or DMA writes @ to the output FIFO occur (not necessary to flush when using @ TIO FIFO as input). F Reserved 6 F Gi_WaitForFirstEventOnGate 2 @ This bit forces the HW to wait for a first event on the gate @ before starting to save data in the FIFO. This can be used to prevent @ the "bad first point" problem. Depending on how the operation @ is setup, waiting for a RE or FE of the gate will ensure @ that the first point returned is in fact the first possible @ valid measurement. For example, for pulse width measurement @ that saves data on the FE of the gate, setting this bit @ to wait for RE will ensure that the first measurement will @ be valid. F Reserved 1 F Gi_WrFifoEnable 1 @ This bit enables the FIFO for output operations. It is necessary @ to enable this bit for DMA operation. When cleared, the data @ for the load registers can be written directly to the load @ registers or through the Gi_AutomaticLoadRegister, which would @ direct the write to the correct load register. F Gi_DoneNotificationEnable 1 @ NOTE: This feature only works then the counter is paired @ with a timing engine for generation of the sample clock. @

    This bit enables the generation of the done notification @ on the input stream. This notification happens after the last @ sample after an SC_TC event has been written to the FIFO. @ After this notification happens, no more data can be written @ until a FIFO reset happens. F Reserved 1 #------------------------------------------------------------------------------- # Gi_SampleClockCountRegister Register Definition R Gi_SampleClockCountRegister 32 0x14 Readable F Gi_SampleClockCount 24 @ This bitfield will reflect the value of the sample clock count. @ This count will reset to 0 when arming the counter and will @ count down, so the value after the first sample clock will @ be 0xFFFFFF. Note that when doing a SW disarm the value @ read will remain being the last valid value registered until @ the counter is armed again reflecting the reset value of 0. F Reserved 8 #------------------------------------------------------------------------------- # Gi_RdFifoRegister Register Definition R Gi_RdFifoRegister 32 0x18 Readable F Gi_RdFifoData 32 @ This bitfield reads from the Counter data FIFO via Programmed @ IO. In order to enable the FIFO, Gi_DMA_Enable needs to be @ set, and Gi_DMA_Write needs to be cleared (set to not write). #------------------------------------------------------------------------------- # Gi_WrFifoRegister Register Definition R Gi_WrFifoRegister 32 0x18 Writable --no-soft-copy true F Gi_WrFifoData 32 @ This bitfield writes to the A and B load registers of the appropriate @ load bank in a FIFO fashion via Programmed IO. In order @ to enable this register, Gi_DMA_Enable needs to be set, @ and Gi_DMA_Write needs to be set. #------------------------------------------------------------------------------- # Gi_SampleClockRegister Register Definition R Gi_SampleClockRegister 16 0x1c Writable F Gi_SampleClockSelect 6 . nCounter::tGi_SampleClockSelect_t @ This bitfield selects the sample clock signal for general-purpose @ counter. F Gi_SampleClockPolarity 1 . nCounter::tGi_Polarity_t @ This bit selects the polarity for the Sample clock signal F Gi_SampleClockLevelMode 1 @ This bit enables level mode for the sample clock. The counter @ will save measurements while the sample clock is active. F Gi_SampleClockMode 3 . nCounter::tGi_SampleClockMode_t @ Selects the mode of operation for the sample clock F Gi_SampleClockPulse 1 Strobe @ When set, this bit generates a pulse on the sample clock signal. @ The SampleClockSelect field needs to be set to the pulse @ bit enumeration for this to work. F Gi_SampleClockSampleMode 1 . nCounter::tGi_SampleClkSampleMode_t @ This bitfield selects the saving timing of the sample clock. @ The options trade off latency vs accurate chronology between @ the sample clock and the sample returned. F Reserved 2 F Gi_SampleClockGateIndependent 1 @ When this bit is set, the sample clock saves data independently @ of the gate. This would be useful for event counting or position @ measurements. This also enables the dual counting mode @ in which the main counter counts source edges and the aux @ counter counts gate edges. #------------------------------------------------------------------------------- # Gi_AuxCtrRegister Register Definition R Gi_AuxCtrRegister 16 0x1e Writable F Gi_AuxCtrMode 3 . nCounter::tGi_AuxCtrMode_t @ This bitfield selects the operation mode of the Aux counter. @ Based on this mode, the Aux counter automatically does the appropriate @ routing and settings for the operation. F Reserved 5 F Gi_AuxCtrLoad 1 Strobe @ Setting this bit to 1 loads the contents of the load register @ A into the Aux counter. This bit is cleared automatically. F Reserved 7 #------------------------------------------------------------------------------- # Gi_AuxCtrLoadA_Register Register Definition R Gi_AuxCtrLoadA_Register 32 0x20 Writable F Gi_AuxCtrLoadA 32 @ Value for loadA register of the Aux Counter #------------------------------------------------------------------------------- # Gi_AuxCtrLoadB_Register Register Definition R Gi_AuxCtrLoadB_Register 32 0x24 Writable F Gi_AuxCtrLoadB 32 @ Value for loadB register of the Aux Counter #------------------------------------------------------------------------------- # Gi_AutomaticLoadRegister Register Definition R Gi_AutomaticLoadRegister 32 0x28 Writable --no-hardware-reset false --no-soft-copy true F Gi_AutoLdRegister 32 @ This field writes to the appropriate load register, which is determined @ by internal pointers, when DMA mode is enabled and @ the Write mode bit is set. It is similar to the write switch @ functionality on the original STC. #------------------------------------------------------------------------------- # Gi_Interrupt1_Register Register Definition R Gi_Interrupt1_Register 32 0x2c Writable --no-soft-copy true F Reserved 3 F Gi_Aux_Ctr_TC_Error_Interrupt_En 1 Strobe @ This strobe bit will enable the Gi_Aux_Ctr_TC_Error event to @ generate an interrupt. F Gi_Aux_Ctr_TC_Interrupt_En 1 Strobe @ This strobe bit will enable the Gi_Aux_Ctr_TC to generate an @ interrupt. F Gi_Disarm_Interrupt_En 1 Strobe @ This strobe bit will enable the Disarm Event to generate an interrupt. F Gi_SampleClockInterruptEn 1 Strobe @ This strobe bit will enable the Sample Clock to generate an interrupt @ if, and only if, that sample clock will end up writing @ data to the FIFO. This means either an error free sample @ clock, or an overrun when not in "stop on error" mode. F Gi_GateSwitchErrorInt_En 1 Strobe @ This bit enables the generation of interrupts when a GateSwitchError @ occurs. F Gi_WritesTooFastErrorEn 1 Strobe @ This bit enables the generation of interrupts when a WritesTooFast @ error occurs. F Gi_DMA_Int_Enable 1 Strobe @ Direct Memory Access Interrupt - This bit enables the generation @ of interrupts for data transfer using the DMA mode circuit. @ As when DMA is enabled, it uses the internal FIFO, and generates @ the interrupt based on its status. This mode of generating @ interrupts should be used to transfer data using interrupts, @ instead of using the gate interrupt. F Gi_Gate_Interrupt_Enable 1 Strobe @ The relevant gate edge is the stop edge in case of level gating, @ or the active edge (both start and stop) in the case of @ edge gating. This bit enables the counter's gate interrupt:

    NOTE @ Do not use this interrupt for data transfer operations @ with the save registers or the FIFO; Use the Gi DMA interrupt @ instead. F Gi_TC_Interrupt_Enable 1 Strobe @ The Gi_TC interrupt occurs on the rising edge of the counter's TC. @ This bit enables the counter's TC interrupt: F Gi_SampleClockOverrunIntEn 1 Strobe @ This bit Enables the generation of an interrupt on an overrun @ error from the Sample Clock signal. F Gi_Gate_Error_Interrupt_Enabled 1 Strobe @ This bit enables the counter's Gate error interrupt. This interrupt @ sets when the latency for acknowledging the Gate interrupt @ was too long and another Gate was received. F Gi_TC_Error_Interrupt_Enable 1 Strobe @ This bit enables the counter's TC error interrupt. This interrupt @ sets when the latency for acknowledging the TC interrupt was @ too long and another TC was received. F Gi_DMA_Error_Interrupt_Enable 1 Strobe @ This bit enables the counter's DMA Error Interrupt. This error is @ the equivalent of a FIFO overflow error for input operations, @ and an underflow error for Output operations. F Reserved 3 F Gi_SampleClockOverrunErrorAck 1 Strobe @ When set, this bit clears the overrun error status bit and the @ overrun interrupt if enabled. If stop on error is set, this @ will also enable the counter to start saving data again. F Gi_SampleClockInterruptAck 1 Strobe @ Setting this bit to 1 clears Gi_SampleClockInterruptSt. This @ bit is cleared automatically. F Gi_Gate_Error_Confirm 1 Strobe @ Setting this bit to 1 clears Gi_Gate_Error_St. This bit is cleared @ automatically. F Gi_TC_Error_Confirm 1 Strobe @ Setting this bit to 1 clears Gi_TC_Error_St. This bit is cleared @ automatically. F Reserved 1 F Gi_Aux_Ctr_TC_Error_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears Aux Ctr TC Error Interrupt_St and @ acknowledges the interrupt. This bit is cleared automatically. F Gi_Aux_Ctr_TC_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears Gi_Aux_Ctr_TC_Interrupt_St and acknowledges @ the interrupt. This bit is cleared automatically. F Gi_Disarm_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears Gi_Disarm_Interrupt_St and acknowledges @ the interrupt. This bit is cleared automatically. F Gi_WritesTooFastErrorAck 1 Strobe @ Setting this bit to 1 clears Gi_WritesTooFastErrSt. This bit @ is cleared automatically. F Gi_GateSwitchError_Ack 1 Strobe @ Setting this bit to 1 clears Gi_GateSwitchError_St. This bit @ is cleared automatically. F Gi_DMA_Error_Ack 1 Strobe @ Setting this bit to 1 clears Gi_DRQ_Error. This bit is cleared @ automatically. F Gi_TC_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears Gi_TC_St and acknowledges the TC @ interrupt request for the counter if the TC interrupt is enabled. @ This bit is cleared automatically. F Gi_Gate_Interrupt_Ack 1 Strobe @ Setting this bit to 1 clears Gi_Gate_Interrupt_St and acknowledges @ the gate interrupt request for the counter if the gate @ interrupt is enabled. This bit is cleared automatically.

    NOTE @ Do not use gate interrupts on the STC3 for interrupt @ driven data transfer. Use the DMA interrupts instead. #------------------------------------------------------------------------------- # Gi_Interrupt2_Register Register Definition R Gi_Interrupt2_Register 32 0x30 Writable --no-soft-copy true F Reserved 3 F Gi_Aux_Ctr_TC_Error_Interrupt_Dis 1 Strobe @ This strobe bit will disable the Gi_Aux_Ctr_TC_Error event to @ generate an interrupt. F Gi_Aux_Ctr_TC_Interrupt_Dis 1 Strobe @ This strobe bit will disable the Gi_Aux_Ctr_TC to generate an @ interrupt. F Gi_Disarm_Interrupt_Dis 1 Strobe @ This strobe bit will disable the Disarm Event to generate an @ interrupt. F Gi_SampleClockInterruptDis 1 Strobe @ This strobe bit will disable the Sample Clock to generate an @ interrupt if, and only if, that sample clock will end up writing @ data to the FIFO. This means either an error free sample @ clock, or an overrun when not in "stop on error" mode. F Gi_GateSwitchErrorInt_Dis 1 Strobe @ This bit disables the generation of interrupts when a GateSwitchError @ occurs. F Gi_WritesTooFastErrorDis 1 Strobe @ This bit disables the generation of interrupts when a WritesTooFast @ error occurs. F Gi_DMA_Int_Disable 1 Strobe @ Direct Memory Access Interrupt - This strobe bit disables the @ generation of interrupts for data transfer using the DMA mode @ circuit. As when DMA is enabled, it uses internal FIFO, and @ generates the interrupt based on its status.

    NOTE @ This mode of generating interrupts should be used to transfer @ data using interrupts, instead of using the gate interrupt. F Gi_Gate_Interrupt_Disable 1 Strobe @ This strobe bit disables the counter's gate interrupt.

    NOTE @ The relevant gate edge is the stop edge in case of @ level gating, or the active edge (both start and stop) in the @ case of edge gating.

    NOTE Do not use this bitfield @ to read data of the save registers or the FIFO. Use the @ Gi DMA interrupt instead. F Gi_TC_Interrupt_Disable 1 Strobe @ This strobe bit disables the counter's TC interrupt.

    NOTE @ The Gi_TC interrupt occurs on the rising edge of the counter's @ TC. F Gi_SampleClockOverrunIntDis 1 Strobe @ This strobe bit disables the generation of an interrupt on an @ overrun error from the Sample Clock signal. F Gi_Gate_Error_Interrupt_Disable 1 Strobe @ This strobe bit disables the counter's Gate error interrupt. This @ interrupt sets when the latency for acknowledging the Gate @ interrupt was too long and another Gate was received. F Gi_TC_Error_Interrupt_Disable 1 Strobe @ This strobe bit disables the counter's TC error interrupt. This interrupt @ sets when the latency for acknowledging the TC interrupt @ was too long and another TC was received. F Gi_DMA_Error_Interrupt_Disable 1 Strobe @ This strobe bit disables the counter's DMA Error Interrupt. This @ error is the equivalent of a FIFO overflow error for input operations, @ and an underflow error for Output operations. F Reserved 3 F Gi_SampleClockOverrunErrorAck2 1 Strobe @ When set, this bit clears the overrun error status bit and the @ overrun interrupt if enabled. If stop on error is set, this @ will also enable the counter to start saving data again. F Gi_SampleClockInterruptAck2 1 Strobe @ Setting this bit to 1 clears Gi_SampleClockInterruptSt. This @ bit is cleared automatically. F Gi_Gate_Error_Confirm2 1 Strobe @ Setting this bit to 1 clears Gi_Gate_Error_St. This bit is cleared @ automatically. F Gi_TC_Error_Confirm2 1 Strobe @ Setting this bit to 1 clears Gi_TC_Error_St. This bit is cleared @ automatically. F Reserved 1 F Gi_Aux_Ctr_TC_Error_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears Aux Ctr TC Error Interrupt_St and @ acknowledges the interrupt. This bit is cleared automatically. F Gi_Aux_Ctr_TC_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears Gi_Aux_Ctr_TC_Interrupt_St and acknowledges @ the interrupt. This bit is cleared automatically. F Gi_Disarm_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears Gi_Disarm_Interrupt_St and acknowledges @ the interrupt. This bit is cleared automatically. F Gi_WritesTooFastErrorAck2 1 Strobe @ Setting this bit to 1 clears Gi_WritesTooFastErrSt. This bit @ is cleared automatically. F Gi_GateSwitchError_Ack2 1 Strobe @ Setting this bit to 1 clears Gi_GateSwitchError_St. This bit @ is cleared automatically. F Gi_DMA_Error_Ack2 1 Strobe @ Setting this bit to 1 clears Gi_DRQ_Error. This bit is cleared @ automatically. F Gi_TC_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears Gi_TC_St and acknowledges the TC @ interrupt request for the counter if the TC interrupt is enabled. @ This bit is cleared automatically. F Gi_Gate_Interrupt_Ack2 1 Strobe @ Setting this bit to 1 clears Gi_Gate_Interrupt_St and acknowledges @ the gate interrupt request for the counter if the gate @ interrupt is enabled. This bit is cleared automatically.

    NOTE @ Do not use gate interrupts on the STC3 for interrupt @ driven data transfer. Use the DMA interrupts instead. #------------------------------------------------------------------------------- # Gi_ABZ_Select_Register Register Definition R Gi_ABZ_Select_Register 32 0x38 Writable F Gi_Z_Select 6 . nCounter::tGi_Z_Select_t @ This field selects the Z signal source during position measurements F Reserved 2 F Gi_B_Select 6 . nCounter::tGi_B_Select_t @ This field selects the B signal source during position measurements @

    NOTE This Mux can also be used to select the @ source for the G_UP_DOWN signal when the Gi_Up_Down bitfield @ is set to Gi_B_High_Up. F Reserved 2 F Gi_A_Select 6 . nCounter::tGi_A_Select_t @ This field selects the A signal source during position measurements F Reserved 10 #------------------------------------------------------------------------------- # Gi_Mode3_Register Register Definition R Gi_Mode3_Register 16 0x3C Writable F Reserved 1 F Reserved 1 F Gi_TimeCoherentSemiperiod 1 @ This bit affects how the counter performs semiperiod measurements @ with the sample clock. The counter will measure a consecutive @ low and high semiperiod, and will return them in the @ order requested (i.e. High, and then low).
    When the bit @ is clear, the high and low semiperiods may be acquired in @ any chronological order. This is the fastest measurement but @ there is uncertainty of the order of the two semiperiods. (For @ example, counter gets a sample clock while measuring the @ low semiperiod, then it finishes that measurement, and then measures @ the high semiperiod. It will return the data then in the @ requested order: High, then low)

    When the bit is set, the @ counter will force the chronological order of the measurements @ to be the same as what was requested. In the same example @ as above, if the counter gets the sample clock while measuring @ the low semiperiod, it will discard the measurement and @ wait until a high semiperiod measurement begins. After that @ is completed it will do a low semiperiod measurement and @ finally it will return the data as requested (High and then @ low). The latency in this mode could be larger. F Reserved 1 F Reserved 1 F Reserved 11 #------------------------------------------------------------------------------- # Gi_Mode2_Register Register Definition R Gi_Mode2_Register 16 0x3E Writable F Gi_HwArmSyncMode 2 . nCounter::tGi_HwArmSyncMode_t @ This bitfield determines the mode of operation of the HW arm @ trigger synchronization. F Gi_CtrOutFifoRegenerationEn 1 @ This bit enables the Counter Output FIFO for regeneration when @ empty. When this bit is enabled, the FIFO will regenerate @ all the data in it upon becoming empty. F Gi_StopOnError 1 @

    For Counter Input Operations: This bit forces the counter @ to stop saving data on an overrun error condition. If not set, @ the counter will ignore the error and will keep saving data @ on valid sample clock signals. The counter will start saving @ data again if the Overrun error is acknowledged.

    @ For Counter Output Operations: This bit prevents the counter @ to generate further switches of waveforms once an underflow @ error has been detected. It does not stop the counter. It @ only stops the waveform switching.

    F Reserved 4 F Gi_WriteOnSwitchRequest 1 @ When this mode is enabled, writes to the counter banks will be @ enabled until a switch is requested (normally using the gate @ as a sample clock). This way, if a write from the CPU happens @ after a switch is requested but before it happens, this @ write won't invalidate the pending switch. In this mode, an @ underflow error happens if at the moment of the switch request, @ the data written to the load registers is not sufficient @ or not coherent. Also a Writes Too Fast error happens if data @ is written twice to the load registers before a new switch @ request is received. F Reserved 1 F Gi_Bank_Switch_Mode 2 . nCounter::tGi_Bank_Switch_Mode_t @ This bit selects the source that controls general purpose counter @ load register bank switching, if bank switching is enabled. F Gi_Bank_Switch_Enable 1 . nCounter::tGi_Bank_Switch_Enable_t @ If the general-purpose counter is not armed, this bit selects @ the bank to which you can write: Bank X if the bit is 0, Bank @ Y if the bit is 1. If the general- purpose counter is armed, @ the value of this bit just before arming enables bank switching: @ disabled if this bit is zero before arming, enabled @ if this bit is 1. It is recommended that after loading all @ banks with data - but before arming - the desired bank switching @ behavior is written to this register. F Reserved 1 F Gi_Up_Down 2 . nCounter::tGi_Up_Down_t @ This bit selects the up/down mode:
    1. Software-selected @ down counting
    2. Software-selected up counting
      3. @
    3. Hardware-selected up/down signal selected by the @ Gi_B signal Mux (see Gi_B_Select). Logic low counts down and @ logic high counts up.
    4. Hardware-selected up/down @ counting controlled by the internal gate value (see G_Gating_Polarity), @ where the active gate level counts up and the inactive @ gate level counts down.
    The selection can @ be safely changed while the counter is counting.