#****************************************************************************** # CHInCh.rbm # # (c) Copyright 2011 # National Instruments Corporation. # All rights reserved. # License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT # Refer to "MHDDK License Agreement.pdf" in the root of this distribution. # # Description: # rbm file for the CHInCh. # This file is autogenerated. Do not modify it directly. # # All lines starting with # or C are comments # All lines starting with T define a register Type # All lines starting with TR define register name, type, offset # All lines starting with F are Fields within the preceding register, # Its name, size, attribute (Strobe|.) and type are defined. # #****************************************************************************** # Declaring RBM as a containable chip object. # This means all instances must specify an offset for it. --containable # Specify the location of the 8 contained DMA channel controller objects --contains AI_DMAChannel 0x2000 DMAController.rbm "tDMAController.h" --contains Counter0DmaChannel 0x2100 DMAController.rbm --contains Counter1DmaChannel 0x2200 DMAController.rbm --contains Counter2DmaChannel 0x2300 DMAController.rbm --contains Counter3DmaChannel 0x2400 DMAController.rbm --contains DI_DMAChannel 0x2500 DMAController.rbm --contains AO_DMAChannel 0x2600 DMAController.rbm --contains DO_DMAChannel 0x2700 DMAController.rbm #=============================================================================== # Register Group Enumerated_Types #=============================================================================== #------------------------------------------------------------------------------- # Enumerated type CHInCh_Signature_t #------------------------------------------------------------------------------- # The value -1072661808 == 0XC0107AD0 E CHInCh_Signature_t V CHInChSignature -1072661808 #------------------------------------------------------------------------------- # Enumerated type Configuration_Value_t #------------------------------------------------------------------------------- E Configuration_Values_t V EEPROMConfig 0x4 V WindowSize 0xC V EEPROMConfigMask 0xF V SMIOConfig 0x40 V WindowEnable 0x80 V SMIOConfigMask 0xF0 V MaxLinkSize 0x200 V PageSize 0x1000 V EEPROMOffset 0x5000 V SMIOOffset 0x6000 #------------------------------------------------------------------------------- # Enumerated type EEPROM_Register_0_Value_t #------------------------------------------------------------------------------- E EEPROM_Register_0_Value_t V EEPROMSettingsRegister0Value 0x14044410 #------------------------------------------------------------------------------- # Enumerated type EEPROM_Register_1_Value_t #------------------------------------------------------------------------------- E EEPROM_Register_1_Value_t V EEPROMSettingsRegister1Value 0x8188008 #------------------------------------------------------------------------------- # Enumerated type EEPROM_Register_2_Value_t #------------------------------------------------------------------------------- E EEPROM_Register_2_Value_t V EEPROMSettingsRegister2Value 0x30006 #------------------------------------------------------------------------------- # Enumerated type SMIO_Register_0_Value_t #------------------------------------------------------------------------------- E SMIO_Register_0_Value_t V SimultaneousRegister0Value 0x404440C #------------------------------------------------------------------------------- # Enumerated type SMIO_Register_1_Value_t #------------------------------------------------------------------------------- E SMIO_Register_1_Value_t V SimultaneousRegister1Value 0x8060102 #------------------------------------------------------------------------------- # Enumerated type SMIO_Register_2_Value_t #------------------------------------------------------------------------------- E SMIO_Register_2_Value_t V SimultaneousRegister2Value 0x8060002 #------------------------------------------------------------------------------- # Enumerated type SMIO_Register_3_Value_t #------------------------------------------------------------------------------- E SMIO_Register_3_Value_t V SimultaneousRegister3Value 0x3 #=============================================================================== # Register Group CHInCh Core Configuration #=============================================================================== #------------------------------------------------------------------------------- # Scrap_Register_t Type Definition T Scrap_Register_t 32 Readable|Writable --no-hardware-reset true --force-default true F SDATA 32 @ This field does not affect hardware operations and resets @ to an unknown value. #------------------------------------------------------------------------------- # CHInCh_Identification_Register Register Definition R CHInCh_Identification_Register 32 0x0 Readable --force-default true F ID 32 . nCHInCh::tCHInCh_Signature_t @ This field is used to identify the CHInCh. #------------------------------------------------------------------------------- # IO_Port_Resource_Description_Register Register Definition R IO_Port_Resource_Description_Register 32 0x10 Readable F Reserved 12 F Reserved 4 F IOMPS 4 @ This field indicates the maximum data payload size in bytes. @ The maximum size is 2^IOMPS bytes. F Reserved 4 F Reserved 8 #------------------------------------------------------------------------------- # Interrupt_Mask_Register Register Definition R Interrupt_Mask_Register 32 0x5C Readable|Writable --no-hardware-reset true --force-default true F Reserved 1 F Reserved 7 F Clear_SMIO_FIFO_Int 1 @ Writing a 1 to this bit disables the SMIO_FIFO line from interrupting the @ host bus. This bit will return a 0 when the interrupt is enabled and a @ 1 when it is disabled. This interrupt is disabled on reset. F Set_SMIO_FIFO_Int 1 @ Writing a 1 to this bit enables the SMIO_FIFO line to interrupt the host bus. @ This bit will return a 1 when the interrupt is enabled and a 0 when it @ is disabled. This interrupt is disabled on reset. F Clear_STC3_Int 1 @ Writing a 1 to this bit disables the STC3 line from interrupting the @ host bus. This bit will return a 0 when the interrupt is enabled and a @ 1 when it is disabled. This interrupt is disabled on reset. F Set_STC3_Int 1 @ Writing a 1 to this bit enables the STC3 line to interrupt the host bus. @ This bit will return a 1 when the interrupt is enabled and a 0 when it @ is disabled. This interrupt is disabled on reset. F Reserved 12 F Reserved 1 F Reserved 1 F Reserved 1 F Reserved 1 F Reserved 1 F Reserved 1 F Clear_CPU_Int 1 @ Writing a 1 to this bit disables interrupts to the host bus. This bit @ will return a 0 when the interrupt is enabled and a 1 when it is @ disabled. The CPU interrupt is disabled on reset. F Set_CPU_Int 1 @ Writing a 1 to this bit enables interrupts to the host bus. This bit @ will return a 1 when the interrupt is enabled and a 0 when it is @ disabled. The CPU interrupt is disabled on reset. #------------------------------------------------------------------------------- # Interrupt_Status_Register Register Definition R Interrupt_Status_Register 32 0x60 Readable --no-soft-copy true # Reading this register returns the interrupt status word for the highest # priority interrupt pending. Reading the volatile offset also clears the # interrupt condition that was reported unless the condition is external. # If the highest priority interrupt pending is from a DMA channel, the # read access will be redirected to the associated Channel Status # Register (CHSR) or Channel Volatile Status Register (CHVSR). See those # register descriptions for the format of DMA interrupt status words. DMA # channel interrupt priority is based on age. The oldest DMA interrupt # pending will have highest priority. F Reserved 9 F SMIO_FIFO_Int 1 @ This read-only bit returns 1 when the SMIO_FIFO interrupt line is asserted and @ external interrupts are the highest priority condition pending. F Reserved 1 F STC3_Int 1 @ This read-only bit returns 1 when the STC3 interrupt line is asserted and @ external interrupts are the highest priority condition pending. F Reserved 4 F Reserved 8 F Reserved 1 F Reserved 1 F Reserved 2 F DMA 1 @ This read-only bit returns 1 when the highest priority notification is @ from a DMA channel. See the Channel Status Register (CHSR) for the @ format of DMA interrupt status words. F External 1 @ This read-only bit returns 1 when the highest priority interrupt is @ external to the CHInCh. More specific interrupt status must be read from @ the STC3 for external interrupts. External interrupt conditions also must @ be cleared in the STC3 – they are not cleared by reading the volatile @ offset in the CHInCh. The external interrupts should be cleared in the @ STC3 before reading this register again because the external interrupt @ conditions will prevent this register from returning lower priority @ conditions – this register will continue to indicate the external @ condition until the IO interrupts are unasserted or disabled in the @ Interrupt Mask Register (IMR). F Additional_Int 1 @ This read-only bit returns 1 when at least one additional interrupt is @ pending beyond the interrupt status word being returned. This allows an @ interrupt service routine to retrieve all pending notifications by @ continuously reading this register until this bit returns 0. F Int 1 @ This read-only bit returns 1 when the CHInCh has a pending interrupt. @ This bit will clear when read from the volatile offset if no additional @ interrupts are pending and the current return value indicates a condition @ that is internal to the CHInCh (the External bit is clear). #------------------------------------------------------------------------------- # Volatile_Interrupt_Status_Register Register Definition R Volatile_Interrupt_Status_Register 32 0x68 Readable --no-soft-copy true F Reserved 9 F Vol_SMIO_FIFO_Int 1 @ This read-only bit returns 1 when the SMIO_FIFO interrupt line is asserted and @ external interrupts are the highest priority condition pending. F Reserved 1 F Vol_STC3_Int 1 @ This read-only bit returns 1 when the STC3 interrupt line is asserted and @ external interrupts are the highest priority condition pending. F Reserved 4 F Reserved 8 F Reserved 1 F Reserved 1 F Reserved 2 F Vol_DMA 1 @ This read-only bit returns 1 when the highest priority notification is @ from a DMA channel. See the Channel Status Register (CHSR) for the @ format of DMA interrupt status words. F Vol_External 1 @ This read-only bit returns 1 when the highest priority interrupt is @ external to the CHInCh. More specific interrupt status must be read from @ the STC3 for external interrupts. External interrupt conditions also must @ be cleared in the STC3 – they are not cleared by reading the volatile @ offset in the CHInCh. The external interrupts should be cleared in the @ STC3 before reading this register again because the external interrupt @ conditions will prevent this register from returning lower priority @ conditions – this register will continue to indicate the external @ condition until the IO interrupts are unasserted or disabled in the @ Interrupt Mask Register (IMR). F Vol_Additional_Int 1 @ This read-only bit returns 1 when at least one additional interrupt is @ pending beyond the interrupt status word being returned. This allows an @ interrupt service routine to retrieve all pending notifications by @ continuously reading this register until this bit returns 0. F Vol_Int 1 @ This read-only bit returns 1 when the CHInCh has a pending interrupt. @ This bit will clear when read from the volatile offset if no additional @ interrupts are pending and the current return value indicates a condition @ that is internal to the CHInCh (the External bit is clear). #------------------------------------------------------------------------------- # Register Definition R Host_Bus_Resource_Control_Register 32 0xA4 Readable|Writable --no-hardware-reset true --force-default true F Reserved 12 F Reserved 1 F Reserved 1 F DMA_MA64 1 @ DMA memory addresses will be 64-bits wide when this bit is set and 32-bits @ wide when it is clear. This bit should not be modified while any DMA channels @ are active. On reset, this bit is clear. F DMA_LA64 1 @ DMA link addresses will be 64-bits wide when this bit is set and 32-bits wide @ when it is clear. This includes link addresses contained in DMA links. This @ bit should not be modified while any DMA channels are active. On reset, this @ bit is clear. F Reserved 4 F Reserved 4 F Reserved 4 F Reserved 1 F Reserved 2 F IO_Master_Enable 1 @ When this bit is set, the CHInCh will process transactions initiated @ by the Stream Circuit. When this bit is clear, the CHInCh will respond @ to such transactions with an error. On reset, this bit is clear. Stream @ transactions can be enabled or disabled with the corresponding DMA @ channel Start bit. #------------------------------------------------------------------------------- # EEPROM_Window_Register Register Definition R EEPROM_Window_Register 32 0xC0 Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F EEPROM_Window_Field 32 @ This field configures the extended EEPROM window for SMIO X Series Devices. #------------------------------------------------------------------------------- # Simultaneous_Window_Register Register Definition R Simultaneous_Window_Register 32 0xC4 Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F Simultaneous_Window_Field 32 @ This field configures the extended register window for SMIO X Series devices. #------------------------------------------------------------------------------- # Window_Control_Register Register Definition R Window_Control_Register 32 0xE0 Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F Window_Control_Field 32 @ This field controls the extended EEPROM window for SMIO X Series devices. #------------------------------------------------------------------------------- # Scrap_Register Register Definition TRA Scrap_Register%d Scrap_Register_t 0x200 1 Scrap%d --step 4 #=============================================================================== # Register Group Configuration Port #=============================================================================== #------------------------------------------------------------------------------- # Configuration_Register Register Definition R Configuration_Register 32 0x514 Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F Configuration_Value 32 @ This field enables the extended registers and EEPROM for SMIO X Series devices. #------------------------------------------------------------------------------- # EEPROM_Register_0 Register Definition R EEPROM_Register_0 32 0x580 Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F EEPROM_Register_0_Value 32 . nCHInCh::tEEPROM_Register_0_Value_t @ This field configures the EEPROM for SMIO X Series devices. #------------------------------------------------------------------------------- # EEPROM_Register_1 Register Definition R EEPROM_Register_1 32 0x584 Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F EEPROM_Register_1_Value 32 . nCHInCh::tEEPROM_Register_1_Value_t @ This field configures the EEPROM for SMIO X Series devices. #------------------------------------------------------------------------------- # EEPROM_Register_2 Register Definition R EEPROM_Register_2 32 0x58C Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F EEPROM_Register_2_Value 32 . nCHInCh::tEEPROM_Register_2_Value_t @ This field configures the EEPROM for SMIO X Series devices. #------------------------------------------------------------------------------- # SMIO_Register_0 Register Definition R SMIO_Register_0 32 0x590 Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F SMIO_Register_0_Value 32 . nCHInCh::tSMIO_Register_0_Value_t @ This field configures the registers for SMIO X Series devices. #------------------------------------------------------------------------------- # SMIO_Register_1 Register Definition R SMIO_Register_1 32 0x594 Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F SMIO_Register_1_Value 32 . nCHInCh::tSMIO_Register_1_Value_t @ This field configures the registers for SMIO X Series devices. #------------------------------------------------------------------------------- # SMIO_Register_2 Register Definition R SMIO_Register_2 32 0x598 Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F SMIO_Register_2_Value 32 . nCHInCh::tSMIO_Register_2_Value_t @ This field configures the registers for SMIO X Series devices. #------------------------------------------------------------------------------- # SMIO_Register_3 Register Definition R SMIO_Register_3 32 0x59C Readable|Writable --force-default true --no-hardware-reset true --no-soft-copy true F SMIO_Register_3_Value 32 . nCHInCh::tSMIO_Register_3_Value_t @ This field configures the registers for SMIO X Series devices. #=============================================================================== # Register Group IO Port 2 Configuration #=============================================================================== #=============================================================================== # Register Group Host Bus Technology #=============================================================================== #------------------------------------------------------------------------------- # PCI_SubSystem_ID_Access_Register Register Definition R PCI_SubSystem_ID_Access_Register 32 0x10AC Readable F SubSystem_Vendor_ID 16 @ This field returns the VID of the sub-system: 0x1093 for @ National Instruments. F SubSystem_Product_ID 16 @ This field returns the PID of the X Series devices: @ use this field to determine which specific X Series model this @ device is.