#****************************************************************************** # BusInterface.rbm # # (c) Copyright 2011 # National Instruments Corporation. # All rights reserved. # License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT # Refer to "MHDDK License Agreement.pdf" in the root of this distribution. # # Description: # rbm file for BusInterface. # This file is autogenerated. Do not modify it directly. # # All lines starting with # or C are comments # All lines starting with T define a register Type # All lines starting with TR define register name, type, offset # All lines starting with F are Fields within the preceding register, # Its name, size, attribute (Strobe|.) and type are defined. # #****************************************************************************** # Declaring RBM as a containable chip object. # This means all instances must specify an offset for it. --containable # Declaring group for register array --generate-include "tBusInterfaceValues.h" #=============================================================================== # Register Group I_O_Bus #=============================================================================== #------------------------------------------------------------------------------- # TIO_Interrupt_Status_Register_t Type Definition T TIO_Interrupt_Status_Register_t 16 Readable F TIO_DmaIrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the DMA Interrupt. This means that this bitfield @ is '1' only if the interrupt occurred, the interrupt is @ enabled, and the interrupt hasn't been acknowledged. F TIO_GateIrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the Gate Interrupt. This means that this bitfield @ is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F TIO_TC_IrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the TC Interrupt. This means that this bitfield @ is '1' only if the interrupt occurred, the interrupt is @ enabled, and the interrupt hasn't been acknowledged. F TIO_SampleClkErrorSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the SampleClkError Interrupt. This means that @ this bitfield is '1' only if the interrupt ocurred, the @ interrupt is enabled, and the interrupt hasn't been acknowledged. F TIO_GateErrorIrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the GateError Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F TIO_TC_ErrorIrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the TC_Error Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F TIO_DMA_ErrorIrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the DMA_Error Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F TIO_WritesTooFast 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the WritesTooFast Interrupt. This means that @ this bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F TIO_GateSwitchErrorIrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the GateSwitchError Interrupt. This means @ that this bitfield is '1' only if the interrupt occurred, the @ interrupt is enabled, and the interrupt hasn't been acknowledged. F SampleClockIrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the Sample Clock Interrupt. This means that @ this bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DisarmEventIrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the Disarm Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AuxCtrTC_IrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the Aux Ctr TC Interrupt. This means that @ this bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AuxCtrTC_ErrorIrqSt 1 @ This bitfield reflects the component of the TIO IRQ vector that @ corresponds to the Aux Ctr TC Error Interrupt. This means @ that this bitfield is '1' only if the interrupt occurred, the @ interrupt is enabled, and the interrupt hasn't been acknowledged. F Reserved 3 #------------------------------------------------------------------------------- # GlobalInterruptStatus_Register Register Definition R GlobalInterruptStatus_Register 16 0x70 Readable F AI_Interrupt_Status 1 @ This bitfield will be set to '1' if any enabled interrupt in @ the AI subsystem occurs and is enabled, therefore causing a @ CPU interrupt. F AO_Interrupt_Status 1 @ This bitfield will be set to '1' if any enabled interrupt in @ the AO subsystem occurs and is enabled, therefore causing a @ CPU interrupt. F G0_Interrupt_Status 1 @ This bitfield will be set to '1' if any enabled interrupt in @ the Counter 0 subsystem occurs and is enabled, therefore causing @ a CPU interrupt. F G1_Interrupt_Status 1 @ This bitfield will be set to '1' if any enabled interrupt in @ the Counter 1 subsystem occurs and is enabled, therefore causing @ a CPU interrupt. F G2_Interrupt_Status 1 @ This bitfield will be set to '1' if any enabled interrupt in @ the Counter 2 subsystem occurs and is enabled, therefore causing @ a CPU interrupt. F G3_Interrupt_Status 1 @ This bitfield will be set to '1' if any enabled interrupt in @ the Counter 3 subsystem occurs and is enabled, therefore causing @ a CPU interrupt. F DI_Interrupt_Status 1 @ This bitfield will be set to '1' if any enabled interrupt in @ the DI subsystem occurs and is enabled, therefore causing a @ CPU interrupt. F DO_Interrupt_Status 1 @ This bitfield will be set to '1' if any enabled interrupt in @ the DO subsystem occurs and is enabled, therefore causing a @ CPU interrupt. F Reserved 1 F Reserved 1 F Gen_Interrupt_Status 1 @ This bitfield will be set to '1' if any enabled interrupt in @ the Generic Group occurs and is enabled, therefore causing a @ CPU interrupt. F Reserved 5 #------------------------------------------------------------------------------- # AI_Interrupt_Status_Register Register Definition R AI_Interrupt_Status_Register 16 0x72 Readable F Reserved 6 F AI_OverflowIrqSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_Overflow Interrupt. This means that @ this bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AI_SC_PreWaitRollOverSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_SC_PreWaitRollOver Interrupt. This means @ that this bitfield is '1' only if the interrupt occurred, @ the interrupt is enabled, and the interrupt hasn't been acknowledged. F AI_ScanOverrunIrqSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_ScanOverrun Interrupt. This means that @ this bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AI_SC_TC_IrqSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_SC_TC Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AI_Start1IrqSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_START1 Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AI_Start2IrqSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_START2 Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AI_StartIrqSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_START Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AI_StopIrqSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_STOP Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AI_OverrunIrqSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_Overrun Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AI_FifoIrqSt 1 @ This bitfield reflects the component of the AI IRQ vector that @ corresponds to the AI_FIFO Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. #------------------------------------------------------------------------------- # AO_Interrupt_Status_Register Register Definition R AO_Interrupt_Status_Register 16 0x74 Readable F Reserved 9 F AO_WriteTooFastIrqSt 1 @ This bitfield reflects the component of the AO IRQ vector that @ corresponds to the AO_WriteTooFast Interrupt. This means that @ this bitfield is '1' only if the interrupt occurred, the @ interrupt is enabled, and the interrupt hasn't been acknowledged. F AO_BC_TC_IrqSt 1 @ This bitfield reflects the component of the AO IRQ vector that @ corresponds to the AO_BC_TC Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AO_Start1IrqSt 1 @ This bitfield reflects the component of the AO IRQ vector that @ corresponds to the AO_START1 Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AO_UpdateIrqSt 1 @ This bitfield reflects the component of the AO IRQ vector that @ corresponds to the AO_UPDATE Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AO_ErrorIrqSt 1 @ This bitfield reflects the component of the AO IRQ vector that @ corresponds to the AO_Error Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AO_UC_TC_IrqSt 1 @ This bitfield reflects the component of the AO IRQ vector that @ corresponds to the AO_UC_TC Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F AO_FifoIrqSt 1 @ This bitfield reflects the component of the AO IRQ vector that @ corresponds to the AO_FIFO Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. #------------------------------------------------------------------------------- # TIO_Interrupt_Status_Register Register Definition TRA TIO_Interrupt_Status_Register%d TIO_Interrupt_Status_Register_t 0x76 4 Counter%d --step 2 #------------------------------------------------------------------------------- # GlobalInterruptEnable_Register Register Definition R GlobalInterruptEnable_Register 32 0x78 Writable --no-soft-copy true F AI_Interrupt_Enable 1 Strobe @ Write '1' to this field to allow all of the interrupts in the AI subsystem to propagate to the CHInCh. F AO_Interrupt_Enable 1 Strobe @ Write '1' to this field to allow all of the interrupts in the AO subsystem to propagate to the CHInCh. F G0_Interrupt_Enable 1 Strobe @ Write '1' to this field to allow all of the interrupts in the Counter 0 subsystem to propagate to the CHInCh. F G1_Interrupt_Enable 1 Strobe @ Write '1' to this field to allow all of the interrupts in the Counter 1 subsystem to propagate to the CHInCh. F G2_Interrupt_Enable 1 Strobe @ Write '1' to this field to allow all of the interrupts in the Counter 2 subsystem to propagate to the CHInCh. F G3_Interrupt_Enable 1 Strobe @ Write '1' to this field to allow all of the interrupts in the Counter 3 subsystem to propagate to the CHInCh. F DI_Interrupt_Enable 1 Strobe @ Write '1' to this field to allow all of the interrupts in the DI subsystem to propagate to the CHInCh. F DO_Interrupt_Enable 1 Strobe @ Write '1' to this field to allow all of the interrupts in the DO subsystem to propagate to the CHInCh. F Reserved 1 F Reserved 1 F Gen_Interrupt_Enable 1 Strobe @ Write '1' to this field to allow all of the interrupts in the Generic Group to propagate to the CHInCh. F Reserved 5 F AI_Interrupt_Disable 1 Strobe @ Write '1' to this field to block all of the interrupts in the AI subsystem from propagating to the CHInCh. F AO_Interrupt_Disable 1 Strobe @ Write '1' to this field to block all of the interrupts in the AO subsystem from propagating to the CHInCh. F G0_Interrupt_Disable 1 Strobe @ Write '1' to this field to block all of the interrupts in the Counter 0 subsystem from propagating to the CHInCh. F G1_Interrupt_Disable 1 Strobe @ Write '1' to this field to block all of the interrupts in the Counter 1 subsystem from propagating to the CHInCh. F G2_Interrupt_Disable 1 Strobe @ Write '1' to this field to block all of the interrupts in the Counter 2 subsystem from propagating to the CHInCh. F G3_Interrupt_Disable 1 Strobe @ Write '1' to this field to block all of the interrupts in the Counter 3 subsystem from propagating to the CHInCh. F DI_Interrupt_Disable 1 Strobe @ Write '1' to this field to block all of the interrupts in the DI subsystem from propagating to the CHInCh. F DO_Interrupt_Disable 1 Strobe @ Write '1' to this field to block all of the interrupts in the DO subsystem from propagating to the CHInCh. F Reserved 1 F Reserved 1 F Gen_Interrupt_Disable 1 Strobe @ Write '1' to this field to block all of the interrupts in the Generic Group from propagating to the CHInCh. F Reserved 5 #------------------------------------------------------------------------------- # DI_Interrupt_Status_Register Register Definition R DI_Interrupt_Status_Register 16 0x7E Readable F DI_ChangeDetectionIrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_ChangeDetectStatus Interrupt. This means @ that this bitfield is '1' only if the interrupt occurred, @ the interrupt is enabled, and the interrupt hasn't been acknowledged. F DI_ChangeDetectionErrorIrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_ChangeDetectError Interrupt. This means @ that this bitfield is '1' only if the interrupt occurred, @ the interrupt is enabled, and the interrupt hasn't been acknowledged. F Reserved 4 F DI_OverflowIrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_Overflow Interrupt. This means that @ this bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DI_SC_PreWaitRollOverSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_SC_PreWaitRollOver Interrupt. This means @ that this bitfield is '1' only if the interrupt occurred, @ the interrupt is enabled, and the interrupt hasn't been acknowledged. F DI_ScanOverrunIrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_ScanOverrun Interrupt. This means that @ this bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DI_SC_TC_IrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_SC_TC Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DI_Start1IrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_START1 Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DI_Start2IrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_START2 Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DI_StartIrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_START Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DI_StopIrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_STOP Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DI_OverrunIrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_Overrun Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DI_FifoIrqSt 1 @ This bitfield reflects the component of the DI IRQ vector that @ corresponds to the DI_FIFO Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. #------------------------------------------------------------------------------- # DO_Interrupt_Status_Register Register Definition R DO_Interrupt_Status_Register 16 0x80 Readable F Reserved 9 F DO_WriteTooFastIrqSt 1 @ This bitfield reflects the component of the DO IRQ vector that @ corresponds to the DO_WriteTooFast Interrupt. This means that @ this bitfield is '1' only if the interrupt occurred, the @ interrupt is enabled, and the interrupt hasn't been acknowledged. F DO_BC_TC_IrqSt 1 @ This bitfield reflects the component of the DO IRQ vector that @ corresponds to the DO_BC_TC Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DO_Start1IrqSt 1 @ This bitfield reflects the component of the DO IRQ vector that @ corresponds to the DO_START1 Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DO_UpdateIrqSt 1 @ This bitfield reflects the component of the DO IRQ vector that @ corresponds to the DO_UPDATE Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DO_ErrorIrqSt 1 @ This bitfield reflects the component of the DO IRQ vector that @ corresponds to the DO_Error Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DO_UC_TC_IrqSt 1 @ This bitfield reflects the component of the DO IRQ vector that @ corresponds to the DO_UC_TC Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. F DO_FifoIrqSt 1 @ This bitfield reflects the component of the DO IRQ vector that @ corresponds to the DO_FIFO Interrupt. This means that this @ bitfield is '1' only if the interrupt occurred, the interrupt @ is enabled, and the interrupt hasn't been acknowledged. #------------------------------------------------------------------------------- # Gen_Interrupt_Status_Register Register Definition R Gen_Interrupt_Status_Register 16 0x86 Readable F WatchdogTimerTriggerSt 1 @ This bitfield reflects the status of the WatchdogTimer interrupt. @ This means that this bitfield is '1' only if the interrupt @ occurred, the interrupt is enabled, and the interrupt hasn't @ been acknowledged. F PLL_OutOfLockEventSt 1 @ This bitfield reflects the status of the PLL_OutOfLock interrupt. @ This means that this bitfield is '1' only if the interrupt @ occurred, the interrupt is enabled, and the interrupt hasn't @ been acknowledged. F Reserved 14