#****************************************************************************** # BrdServices.rbm # # (c) Copyright 2011 # National Instruments Corporation. # All rights reserved. # License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT # Refer to "MHDDK License Agreement.pdf" in the root of this distribution. # # Description: # rbm file for BrdServices. # This file is autogenerated. Do not modify it directly. # # All lines starting with # or C are comments # All lines starting with T define a register Type # All lines starting with TR define register name, type, offset # All lines starting with F are Fields within the preceding register, # Its name, size, attribute (Strobe|.) and type are defined. # #****************************************************************************** # Declaring RBM as a containable chip object. # This means all instances must specify an offset for it. --containable #=============================================================================== # Register Group Enumerated_Types #=============================================================================== #------------------------------------------------------------------------------- # Enumerated type STC3_Signature_t #------------------------------------------------------------------------------- E STC3_Signature_t V STC3_RevBSignature 0x08050501 V STC3_RevASignature 0x08050509 #------------------------------------------------------------------------------- # Enumerated type BrdSrv_SCXI_Force_AI_EXTMUX_CLK_Width_t #------------------------------------------------------------------------------- E BrdSrv_SCXI_Force_AI_EXTMUX_CLK_Width_t V AI_ExtMux_Clk_250ns 0 V AI_ExtMux_Clk_500ns 1 #------------------------------------------------------------------------------- # Enumerated type BrdSrv_SCXI_HW_Serial_Timebase_t #------------------------------------------------------------------------------- E BrdSrv_SCXI_HW_Serial_Timebase_t V ScxiSrc_100kHz 0 V ScxiSrc_FastTB 1 #------------------------------------------------------------------------------- # Enumerated type BrdSrv_SCXI_Trig1_Output_Select_t #------------------------------------------------------------------------------- E BrdSrv_SCXI_Trig1_Output_Select_t V ScxiTrig1_Out_PFI0 0 V ScxiTrig1_Out_PFI1 1 V ScxiTrig1_Out_PFI2 2 V ScxiTrig1_Out_PFI3 3 V ScxiTrig1_Out_PFI4 4 V ScxiTrig1_Out_PFI5 5 V ScxiTrig1_Out_PFI6 6 V ScxiTrig1_Out_PFI7 7 V ScxiTrig1_Out_PFI8 8 V ScxiTrig1_Out_PFI9 9 V ScxiTrig1_Out_PFI10 10 V ScxiTrig1_Out_PFI11 11 V ScxiTrig1_Out_PFI12 12 V ScxiTrig1_Out_PFI13 13 V ScxiTrig1_Out_PFI14 14 V ScxiTrig1_Out_PFI15 15 V ScxiTrig1_Out_RTSI0 16 V ScxiTrig1_Out_RTSI1 17 V ScxiTrig1_Out_RTSI2 18 V ScxiTrig1_Out_RTSI3 19 V ScxiTrig1_Out_RTSI4 20 V ScxiTrig1_Out_RTSI5 21 V ScxiTrig1_Out_RTSI6 22 V ScxiTrig1_Out_RTSI7 23 V ScxiTrig1_Out_AI_Start 24 V ScxiTrig1_Out_Low 31 #------------------------------------------------------------------------------- # Enumerated type BrdSrv_WatchdogTimerExtSrcSel_t #------------------------------------------------------------------------------- E BrdSrv_WatchdogTimerExtSrcSel_t V WdtSrc_RTSI0 0 V WdtSrc_RTSI1 1 V WdtSrc_RTSI2 2 V WdtSrc_RTSI3 3 V WdtSrc_RTSI4 4 V WdtSrc_RTSI5 5 V WdtSrc_RTSI6 6 V WdtSrc_RTSI7 7 #------------------------------------------------------------------------------- # Enumerated type BrdSrv_WatchdogTimerStateMachineSt_t #------------------------------------------------------------------------------- E BrdSrv_WatchdogTimerStateMachineSt_t V WdtSt_SynchReset 0 V WdtSt_CountDownFeed 1 V WdtSt_CountDownFood 2 V WdtSt_Sleeping 3 V WdtSt_ExpiredPulse 5 V WdtSt_Expired 6 #=============================================================================== # Register Group GenIRQ #=============================================================================== #------------------------------------------------------------------------------- # Gen_Interrupt1_Register Register Definition R Gen_Interrupt1_Register 32 0x70 Writable --no-soft-copy true F WDT_TriggerIRQ_Enable 1 Strobe @ This strobe bit enables the WDT_TriggerIRQ interrupt. F PLL_OutOfLockIRQ_Enable 1 Strobe @ This strobe bit enables the PLL_OutOfLockIRQ interrupt. F Reserved 14 F WDT_TriggerIRQ_Ack 1 Strobe @ This bit clears the WDT_TriggerIRQ Interrupt event and acknowledges @ the interrupt. F PLL_OutOfLockIRQ_Ack 1 Strobe @ This bit clears the PLL_OutOfLockIRQ Interrupt event and acknowledges @ the interrupt. F Reserved 14 #------------------------------------------------------------------------------- # Gen_Interrupt2_Register Register Definition R Gen_Interrupt2_Register 32 0x74 Writable --no-soft-copy true F WDT_TriggerIRQ_Disable 1 Strobe @ This strobe bit disables the WDT_TriggerIRQ interrupt. F PLL_OutOfLockIRQ_Disable 1 Strobe @ This strobe bit disables the PLL_OutOfLockIRQ interrupt. F Reserved 14 F WDT_TriggerIRQ_Ack2 1 Strobe @ This bit clears the WDT_TriggerIRQ Interrupt event and acknowledges @ the interrupt. F PLL_OutOfLockIRQ_Ack2 1 Strobe @ This bit clears the PLL_OutOfLockIRQ Interrupt event and acknowledges @ the interrupt. F Reserved 14 #=============================================================================== # Register Group Global #=============================================================================== #------------------------------------------------------------------------------- # ScratchPadRegister Register Definition R ScratchPadRegister 32 0x04 Readable|Writable F Scratch_Pad 32 @ This is a simple readable writable register that is included @ for self test. #------------------------------------------------------------------------------- # Signature_Register Register Definition R Signature_Register 32 0x60 Readable F STC3_Revision 32 @

This bitfield contains the revision data of the chip in the @ form YYMMDDHH. YY = year (20YY). MM = month. DD = day. HH @ = Hour (24 hour time).

The value of this register @ is 0x08050509 for revision A STC3 ASICs and 0x08050501 for @ revision B STC3 ASICs.

#------------------------------------------------------------------------------- # Joint_Reset_Register Register Definition R Joint_Reset_Register 16 0x64 Writable --no-soft-copy true F Software_Reset 1 Strobe @ Setting this bit to 1 resets the STC3 endpoint. One difference @ between a HW reset and a SW reset is that personality @ bits are NOT cleared on a Software reset. This bit is a @ strobe and clears itself. F Reserved 15 #------------------------------------------------------------------------------- # TimeSincePowerUpRegister Register Definition R TimeSincePowerUpRegister 32 0x64 Readable F TimeSincePowerUpValue 32 @ This number indicates the time since the last reset on the bus. @ The time can be calculated as 2^16 * (Osc Period) * N. With @ a 100MHz oscillator, this number comes out to be 0.65536 @ ms*N. #=============================================================================== # Register Group PWM #=============================================================================== #------------------------------------------------------------------------------- # GenPwmPageSpec_i Type Definition T GenPwmPageSpec_i 8 Writable F GenPwmNumPagesSpec_i 8 @ This field sets the number of page bits that the current PWM @ is going to operate with. This number is programmable from 0 @ to 10. Programming a number outside this range is invalid and @ could cause wrong behavior. The number of page bits determines @ the number of windows the PWM uses to distribute the ones @ in a normal PWM period. The number of windows is 2^NumPages. #------------------------------------------------------------------------------- # Gen_PWM_i Type Definition T Gen_PWM_i 16 Writable F Gen_PWM_i_Duty_Cycle 16 @ These PWM's have programmable frequency and page bits. The fundamental @ frequency is 50 MHz.
PWM n Duty Cycle @ -
The duty cycle of the PWM output is expressed by @ the formula:

DutyCycle = 100% *(PWM n Duty Cycle/65536) @

NOTE: 0 is reset value and represents @ 0% duty cycle, and 65535 represent the maximum duty cycle @ possible (99.9985%)

The number of page bits (determined @ by the GenPwmNumPagesSpec_i bitfield) control how @ the high time is spread on the period of the signal. The higher @ the page bits, the more spread the high time will be. This @ increments the effective frequency of the signal making it @ easier to filter. The tradeoff is that it makes the PWM less @ linear due to the difference in transition times between @ rising and falling edges. #------------------------------------------------------------------------------- # GenPwmPageSpec_i Register Definition TRA GenPwmPageSpec_i%d GenPwmPageSpec_i 0x18 7 GenPwmPageSpec%d --step 1 #------------------------------------------------------------------------------- # Gen_PWM_i Register Definition TRA Gen_PWM_i%d Gen_PWM_i 0x24 7 PWM%d --step 2 #=============================================================================== # Register Group SCXI #=============================================================================== #------------------------------------------------------------------------------- # SCXI_Serial_Data_In_Register Register Definition R SCXI_Serial_Data_In_Register 8 0x10 Readable F SCXI_Data_In 8 Strobe @ This register represents the last 8 bits of data shifted in through @ the SCXI MISO line. Data will be shifted in on the rising @ edge of SPIClk regardless of whether it is in hardware @ or software timed mode. #------------------------------------------------------------------------------- # SCXI_Serial_Data_Out_Register Register Definition R SCXI_Serial_Data_Out_Register 8 0x10 Writable --no-soft-copy true F SCXI_Data_Out 8 Strobe @ When the hardware communications is enabled, this register should @ be written with the data to be shifted. When hardware communications @ is disabled, bit 0 of this register will be output @ on the SCXI MOSI line. #------------------------------------------------------------------------------- # SCXI_Control_Register Register Definition R SCXI_Control_Register 8 0x12 Readable|Writable --initial-value 0xA1 F SCXI_SW_SPIClk 1 @ This register is output onto the SCXI SPIClk line when the HW_Serial_Enable @ bit is written to 0. F SCXI_Back_Plane_MISO_Enable 1 @ When this bit is set to 1, the back plane MISO signal will be @ used to shift data into the SCXI Input register. When both @ this bit and the SCXI_Front_Panel_MISO_Enable bit are set, the @ Input register will shift in the logical AND of the Front @ and Back MISO signals. F SCXI_Front_Panel_MISO_Enable 1 @ When this bit is set to 1, the front panel MISO signal will be @ used to shift data into the SCXI Input register. When both @ this bit and the SCXI_Back_Plane_MISO_Enable bit are set, the @ Input register will shift in the logical AND of the Front @ and Back MISO signals. F SCXI_Intr 1 @ This register is output onto the SCXI Intr line. F SCXI_D_A 1 @ This register is output onto the SCXI D_A line. F SCXI_HW_Serial_Timebase 1 . nBrdServices::tBrdSrv_SCXI_HW_Serial_Timebase_t @ Determines the HW_Serial_Timebase: F SCXI_HW_Serial_Start 1 Strobe @ Writing 1 to this bit starts an SCXI Shift Out as long as HW_Serial_Enable @ is set. The SCXI_Shift_In_Prog bit should be read @ to make sure there is no Serial Shift occurring before writing @ this bit. F SCXI_HW_Serial_Enable 1 @ Set this bit to enable the HW_Serial logic. When enabled, the @ SPI_Clk comes from HW_Serial logic #------------------------------------------------------------------------------- # SCXI_Output_Enable_Register Register Definition R SCXI_Output_Enable_Register 8 0x14 Readable|Writable F SCXI_Dedicated_Output_Enable 1 @ This bit enables the output for the SCXI D_A, Intr, and MOSI @ lines that go to the dedicated SCXI lines on the PXI backplane. F SCXI_Trig1_Output_Enable 1 @ This bit enables the SCXI_Trig1 signal for output. F SCXI_Trig0_Output_Enable 1 @ This bit enables the SCXI_Trig0 signal for output. F SCXI_Trig1_Output_Select 5 . nBrdServices::tBrdSrv_SCXI_Trig1_Output_Select_t @ This bitfield selects the source for SCXI_Trig1: #------------------------------------------------------------------------------- # SCXI_Status_Register Register Definition R SCXI_Status_Register 8 0x16 Readable F SCXI_Shift_In_Prog 1 Strobe @ This bit will read a 1 when the Hardware SCXI Communications @ Engine is shifting data. This bit should be polled for 0 before @ starting another SCXI shift operation with the SCXI_HW_Serial_Start @ bit. F Reserved 7 #------------------------------------------------------------------------------- # SCXI_Mux_Clock_Register Register Definition R SCXI_Mux_Clock_Register 8 0x16 Writable F SCXI_Force_AI_EXTMUX_CLK_Width 1 . nBrdServices::tBrdSrv_SCXI_Force_AI_EXTMUX_CLK_Width_t @ This bit affects the AI_ExternalMux_Clk signal when the AI_EXTMUX_CLK_Pulse_Width @ bit is set to 0. F Reserved 5 F Reserved 1 F Reserved 1 #=============================================================================== # Register Group WatchdogTimer #=============================================================================== #------------------------------------------------------------------------------- # WatchdogStatusRegister Register Definition R WatchdogStatusRegister 32 0x68 Readable F WatchdogSM_State 3 . nBrdServices::tBrdSrv_WatchdogTimerStateMachineSt_t @ This bitfield reflects the status of the Watchdog state machine. F Reserved 5 F WatchdogExpiredCnt 8 @ This bitfield reflects how many times the Watchdog Timer has @ expired since the last reset. This will include internal and @ external triggers if enabled. F Reserved 16 #------------------------------------------------------------------------------- # WatchdogTimeoutRegister Register Definition R WatchdogTimeoutRegister 32 0x68 Writable F WatchdogTimeoutValue 32 @ This bitfield sets the timeout value for the Watchdog timer @ in the STC3. The value represents the number of bus clock periods @ that the counter will count before expiring if it does @ not get acknowledged from SW. When the timer expires, it can @ generate a pulse that can be exported to I/O resources (such @ as AO or DO), and to RTSI. The modules receiving this pulse @ can take action such as placing the outputs on a safe state. #------------------------------------------------------------------------------- # WatchdogConfiguration Register Definition R WatchdogConfiguration 16 0x6C Writable F WatchdogExtTrigSel 3 . nBrdServices::tBrdSrv_WatchdogTimerExtSrcSel_t @ This bitfield selects the source for the external trigger source. F Reserved 4 F WatchdogExtTrigPol 1 @ This bit selects the polarity of the external trigger signal. @ Set to zero for active high, and to one for active low. F WatchdogExtTrigEn 1 @ This bit enables the generation of an Expired Trigger pulse from @ the external trigger source. When this bit is set, the Watchdog Timer @ will generate a trigger any time that it detects @ a rising edge in the selected external trigger (after polarity @ selection) F WatchdogIntTrigEn 1 @ This bit enables the generation of Expired trigger from the internal @ counter. When this bit is set, any time the timer gets @ to zero, the Watchdog Timer will generate an expired trigger @ pulse. F Reserved 6 #------------------------------------------------------------------------------- # WatchdogControl Register Definition R WatchdogControl 16 0x6E Writable --no-soft-copy true F WatchdogCommand 16 Strobe @ This register must be pinged with alternating 0xFEED and 0xF00D @ commands to keep the Watchdog from expiring. The expiration @ interval is set by the WatchdogTimeout Register. After reset @ 0x5678 should be used to start the sequence. Writing 0xFEED @ or 0xF00D out of sequence causes an immediate expiration @ of the timer. 0x1234 can be written to pause the Watchdog. @ 0x5678 can be used to resume the Watchdog. After resuming from @ the pause the device expects the 0xFEED/0xF00D sequence @ to re-start. That is, 0xFEED first. You can force the timer @ to expire immediately by writing 0xDEAD. Once the Watchdog Timer @ has expired, there are several ways to acknowledge and @ continue. If in the expired state, the WDT receives the 0x1234 @ command, then it goes to the paused state. From there it @ can be restarted by writing 0x5678. Alternatively, one can write @ the 0xACED command to immediately restart the WDT. In either @ case the WDT will start with a fresh count that would re-start @ the 0xFEED/0xF00D sequence (would expect 0xFEED first).