#****************************************************************************** # AO.rbm # # (c) Copyright 2011 # National Instruments Corporation. # All rights reserved. # License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT # Refer to "MHDDK License Agreement.pdf" in the root of this distribution. # # Description: # rbm file for AO. # This file is autogenerated. Do not modify it directly. # # All lines starting with # or C are comments # All lines starting with T define a register Type # All lines starting with TR define register name, type, offset # All lines starting with F are Fields within the preceding register, # Its name, size, attribute (Strobe|.) and type are defined. # #****************************************************************************** # Declaring RBM as a containable chip object. # This means all instances must specify an offset for it. --containable # Specify the location of the contained OutTimer object # contained within the AO engine. --contains AO_Timer 0x70 OutTimer.rbm "tOutTimer.h" --generate-include "tAOValues.h" #=============================================================================== # Register Group Enumerated_Types #=============================================================================== #------------------------------------------------------------------------------- # Enumerated type AO_Bipolar_t #------------------------------------------------------------------------------- E AO_Bipolar_t V Bipolar 1 #------------------------------------------------------------------------------- # Enumerated type AO_External_Gate_Select_t #------------------------------------------------------------------------------- E AO_External_Gate_Select_t V Gate_Disabled 0 V Gate_PFI0 1 V Gate_PFI1 2 V Gate_PFI2 3 V Gate_PFI3 4 V Gate_PFI4 5 V Gate_PFI5 6 V Gate_PFI6 7 V Gate_PFI7 8 V Gate_PFI8 9 V Gate_PFI9 10 V Gate_RTSI0 11 V Gate_RTSI1 12 V Gate_RTSI2 13 V Gate_RTSI3 14 V Gate_RTSI4 15 V Gate_RTSI5 16 V Gate_RTSI6 17 V Gate_PXIe_DStarA 18 V Gate_PXIe_DStarB 19 V Gate_Star_Trigger 20 V Gate_PFI10 21 V Gate_PFI11 22 V Gate_PFI12 23 V Gate_PFI13 24 V Gate_PFI14 25 V Gate_PFI15 26 V Gate_RTSI7 27 V Gate_Analog_Trigger 30 V Gate_Low 31 V Gate_G0_Out 32 V Gate_G1_Out 33 V Gate_G2_Out 34 V Gate_G3_Out 35 V Gate_G0_Gate 36 V Gate_G1_Gate 37 V Gate_G2_Gate 38 V Gate_G3_Gate 39 V Gate_AI_Gate 40 V Gate_DI_Gate 41 V Gate_DO_Gate 44 V Gate_IntTriggerA0 53 V Gate_IntTriggerA1 54 V Gate_IntTriggerA2 55 V Gate_IntTriggerA3 56 V Gate_IntTriggerA4 57 V Gate_IntTriggerA5 58 V Gate_IntTriggerA6 59 V Gate_IntTriggerA7 60 #------------------------------------------------------------------------------- # Enumerated type AO_Polarity_t #------------------------------------------------------------------------------- E AO_Polarity_t V Rising_Edge 0 V Falling_Edge 1 #------------------------------------------------------------------------------- # Enumerated type AO_START1_Select_t #------------------------------------------------------------------------------- E AO_START1_Select_t V Start1_Pulse 0 V Start1_PFI0 1 V Start1_PFI1 2 V Start1_PFI2 3 V Start1_PFI3 4 V Start1_PFI4 5 V Start1_PFI5 6 V Start1_PFI6 7 V Start1_PFI7 8 V Start1_PFI8 9 V Start1_PFI9 10 V Start1_RTSI0 11 V Start1_RTSI1 12 V Start1_RTSI2 13 V Start1_RTSI3 14 V Start1_RTSI4 15 V Start1_RTSI5 16 V Start1_RTSI6 17 V Start1_AI_Start2 18 V Start1_AI_Start1 19 V Start1_Star_Trigger 20 V Start1_PFI10 21 V Start1_PFI11 22 V Start1_PFI12 23 V Start1_PFI13 24 V Start1_PFI14 25 V Start1_PFI15 26 V Start1_RTSI7 27 V Start1_PXIe_DStarA 28 V Start1_PXIe_DStarB 29 V Start1_Analog_Trigger 30 V Start1_Low 31 V Start1_G0_Out 32 V Start1_G1_Out 33 V Start1_G2_Out 34 V Start1_G3_Out 35 V Start1_DIO_ChgDetect 36 V Start1_DI_Start1 37 V Start1_DI_Start2 38 V Start1_DO_Start1 43 V Start1_IntTriggerA0 53 V Start1_IntTriggerA1 54 V Start1_IntTriggerA2 55 V Start1_IntTriggerA3 56 V Start1_IntTriggerA4 57 V Start1_IntTriggerA5 58 V Start1_IntTriggerA6 59 V Start1_IntTriggerA7 60 V Start1_FifoCondition 61 #------------------------------------------------------------------------------- # Enumerated type AO_UPDATE_Source_Select_t #------------------------------------------------------------------------------- E AO_UPDATE_Source_Select_t V Update_UI_TC 0 V Update_PFI0 1 V Update_PFI1 2 V Update_PFI2 3 V Update_PFI3 4 V Update_PFI4 5 V Update_PFI5 6 V Update_PFI6 7 V Update_PFI7 8 V Update_PFI8 9 V Update_PFI9 10 V Update_RTSI0 11 V Update_RTSI1 12 V Update_RTSI2 13 V Update_RTSI3 14 V Update_RTSI4 15 V Update_RTSI5 16 V Update_RTSI6 17 V Update_G0_Out 18 V Update_G1_Out 19 V Update_Star_Trigger 20 V Update_PFI10 21 V Update_PFI11 22 V Update_PFI12 23 V Update_PFI13 24 V Update_PFI14 25 V Update_PFI15 26 V Update_RTSI7 27 V Update_G2_Out 28 V Update_G3_Out 29 V Update_Analog_Trigger 30 V Update_Low 31 V Update_PXIe_DStarA 32 V Update_PXIe_DStarB 33 V Update_DIO_ChgDetect 34 V Update_G0_SampleClk 35 V Update_G1_SampleClk 36 V Update_G2_SampleClk 37 V Update_G3_SampleClk 38 V Update_AI_Convert 39 V Update_AI_Start 40 V Update_DI_Convert 41 V Update_DO_Update 44 V Update_IntTriggerA0 53 V Update_IntTriggerA1 54 V Update_IntTriggerA2 55 V Update_IntTriggerA3 56 V Update_IntTriggerA4 57 V Update_IntTriggerA5 58 V Update_IntTriggerA6 59 V Update_IntTriggerA7 60 V Update_AutoUpdate 61 #------------------------------------------------------------------------------- # Enumerated type AO_Update_Mode_t #------------------------------------------------------------------------------- E AO_Update_Mode_t V Immediate 0 V Timed 1 #=============================================================================== # Register Group AO #=============================================================================== #------------------------------------------------------------------------------- # AO_Config_Bank_t Type Definition T AO_Config_Bank_t 8 Writable --no-hardware-reset false --initial-value 0xBF F AO_Offset 3 @ Sets the offset select for Bank i F AO_Reference 3 @ Sets the reference select for Bank i F AO_Update_Mode 1 . nAO::tAO_Update_Mode_t @ This bit determines the update mode for Bank i F AO_Bipolar 1 . nAO::tAO_Bipolar_t @ This bit sets AO Bank i in Bipolar mode #------------------------------------------------------------------------------- # AO_DacShadow_t Type Definition T AO_DacShadow_t 32 Readable F AO_DacShadow_Bitfield 32 @ This register returns the last value that has been updated on @ the DACi. The value returned by this register needs to be masked @ by the resolution of the DAC. The data is LSB aligned. @ So, for a 16 bit DAC, only bits 0-15 should be considered. #------------------------------------------------------------------------------- # AO_Direct_Data_t Type Definition T AO_Direct_Data_t 32 Writable --no-soft-copy true --no-hardware-reset true F AO_Direct_Data_Bitfield 32 Strobe @ This register is used to write data directly to DACi. #------------------------------------------------------------------------------- # AO_DacShadow Register Definition TRA AO_DacShadow%d AO_DacShadow_t 0x0 8 DAC_Shadow%d --step 4 #------------------------------------------------------------------------------- # AO_Direct_Data Register Definition TRA AO_Direct_Data%d AO_Direct_Data_t 0x0 16 DAC%d --step 4 #------------------------------------------------------------------------------- # AO_Order_Config_Data_Register Register Definition R AO_Order_Config_Data_Register 32 0x40 Writable --no-soft-copy true --no-hardware-reset false F AO_Waveform_Bitfield_Order 4 @ This bitfield sets the order of all the channels in the generation. @ This field acts as the data input for an order configuration @ FIFO. Sequential writes to this register will set the @ order of the waveform, with the first channel written being @ the first one on the waveform etc. Make sure the order configuration @ FIFO is cleared before starting the sequence of writes. @ All writes to this register must be performed during @ a configuration cycle and no writes are allowed outside configuration. F Reserved 28 #------------------------------------------------------------------------------- # AO_Config_Control_Register Register Definition R AO_Config_Control_Register 32 0x44 Writable --no-soft-copy true F AO_Waveform_Order_Clear 1 Strobe @ This bitfield clears the configuration FIFO for the AO (which @ holds the order for the waveform channels). This bit should @ be set before writing the order channels for a new waveform @ generation. This bit should only be set as part of a configuration @ cycle. F Reserved 31 #------------------------------------------------------------------------------- # AO_Trigger_Select_Register Register Definition R AO_Trigger_Select_Register 32 0x48 Writable F Reserved 8 F AO_External_Gate_Enable 1 @ Setting this bit to 1 enables external gating for the analog @ output group. F AO_External_Gate_Polarity 1 @ This bit selects the polarity of the analog output external gate @ signal. When set to 0 the gate is Active high (high enables @ operation). When set to 1, the gate is Active low (low enables @ operation) F AO_External_Gate_Select 6 . nAO::tAO_External_Gate_Select_t @ This bit enables and selects the external gate F AO_START1_Edge 1 @ This bit enables edge detection of the AO_START1 trigger. This @ bit should normally be set to 1. Set this bit to 1 if AO_START1_Select @ is 0. F AO_START1_Polarity 1 . nAO::tAO_Polarity_t @ This bit determines the polarity of AO_START1 trigger F AO_START1_Select 6 . nAO::tAO_START1_Select_t @ This bitfield selects the AO_START1 trigger F Reserved 1 F AO_UPDATE_Source_Polarity 1 . nAO::tAO_Polarity_t @ This bit selects the active edge of the AO_UPDATE source (the @ signal that is selected by AO_UPDATE_Source_Select). You must @ set this bit to 0 in the internal AO_UPDATE mode. F AO_UPDATE_Source_Select 6 . nAO::tAO_UPDATE_Source_Select_t @ This bitfield selects the AO_UPDATE source. When you set this @ bit to 0, the STC3 is in the internal AO_UPDATE mode. When you @ select any other signal as the AO_UPDATE source, the STC3 @ is in the external AO_UPDATE mode. #------------------------------------------------------------------------------- # AO_Config_Bank Register Definition TRA AO_Config_Bank%d AO_Config_Bank_t 0x4C 8 Bank%d --step 1 #------------------------------------------------------------------------------- # AO_FIFO_Data_Register Register Definition R AO_FIFO_Data_Register 32 0x58 Writable --no-soft-copy true F AO_FIFO_Data 32 Strobe @ This register is used to load data into the AO data FIFO. #------------------------------------------------------------------------------- # AO_FIFO_Status_Register Register Definition R AO_FIFO_Status_Register 32 0x58 Readable F AO_FIFO_Status 32 @ This bitfield represents the amount of data that remains in the @ AO data FIFO.