#****************************************************************************** # AI.rbm # # (c) Copyright 2011 # National Instruments Corporation. # All rights reserved. # License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT # Refer to "MHDDK License Agreement.pdf" in the root of this distribution. # # Description: # rbm file for AI. # This file is autogenerated. Do not modify it directly. # # All lines starting with # or C are comments # All lines starting with T define a register Type # All lines starting with TR define register name, type, offset # All lines starting with F are Fields within the preceding register, # Its name, size, attribute (Strobe|.) and type are defined. # #****************************************************************************** # Declaring RBM as a containable chip object. # This means all instances must specify an offset for it. --containable # Specify the location of the contained InTimer object # contained within the AI engine. --contains AI_Timer 0x40 InTimer.rbm "tInTimer.h" --generate-include "tAIValues.h" #=============================================================================== # Register Group Enumerated_Types #=============================================================================== #------------------------------------------------------------------------------- # Enumerated type AI_Config_Bank_t #------------------------------------------------------------------------------- E AI_Config_Bank_t V Bank0 0 V Bank1 1 #------------------------------------------------------------------------------- # Enumerated type AI_Config_Channel_Type_t #------------------------------------------------------------------------------- E AI_Config_Channel_Type_t V Loopback 0 V Differential 1 V NRSE 2 V RSE 3 V Internal 5 #------------------------------------------------------------------------------- # Enumerated type AI_Disabled_Enabled_t #------------------------------------------------------------------------------- E AI_Disabled_Enabled_t V Disabled 0 V Enabled 1 #------------------------------------------------------------------------------- # Enumerated type AI_External_Gate_Select_t #------------------------------------------------------------------------------- E AI_External_Gate_Select_t V Gate_Disabled 0 V Gate_PFI0 1 V Gate_PFI1 2 V Gate_PFI2 3 V Gate_PFI3 4 V Gate_PFI4 5 V Gate_PFI5 6 V Gate_PFI6 7 V Gate_PFI7 8 V Gate_PFI8 9 V Gate_PFI9 10 V Gate_RTSI0 11 V Gate_RTSI1 12 V Gate_RTSI2 13 V Gate_RTSI3 14 V Gate_RTSI4 15 V Gate_RTSI5 16 V Gate_RTSI6 17 V Gate_PXIe_DStarA 18 V Gate_PXIe_DStarB 19 V Gate_Star_Trigger 20 V Gate_PFI10 21 V Gate_PFI11 22 V Gate_PFI12 23 V Gate_PFI13 24 V Gate_PFI14 25 V Gate_PFI15 26 V Gate_RTSI7 27 V Gate_Analog_Trigger 30 V Gate_Low 31 V Gate_G0_Out 32 V Gate_G1_Out 33 V Gate_G2_Out 34 V Gate_G3_Out 35 V Gate_G0_Gate 36 V Gate_G1_Gate 37 V Gate_G2_Gate 38 V Gate_G3_Gate 39 V Gate_DI_Gate 40 V Gate_AO_Gate 43 V Gate_DO_Gate 44 V Gate_IntTriggerA0 53 V Gate_IntTriggerA1 54 V Gate_IntTriggerA2 55 V Gate_IntTriggerA3 56 V Gate_IntTriggerA4 57 V Gate_IntTriggerA5 58 V Gate_IntTriggerA6 59 V Gate_IntTriggerA7 60 #------------------------------------------------------------------------------- # Enumerated type AI_FifoWidth_t #------------------------------------------------------------------------------- E AI_FifoWidth_t V TwoByteFifo 0 V FourByteFifo 1 #------------------------------------------------------------------------------- # Enumerated type AI_Polarity_t #------------------------------------------------------------------------------- E AI_Polarity_t V Active_High_Or_Rising_Edge 0 V Active_Low_Or_Falling_Edge 1 #------------------------------------------------------------------------------- # Enumerated type AI_START1_Select_t #------------------------------------------------------------------------------- E AI_START1_Select_t V Start1_SW_Pulse 0 V Start1_PFI0 1 V Start1_PFI1 2 V Start1_PFI2 3 V Start1_PFI3 4 V Start1_PFI4 5 V Start1_PFI5 6 V Start1_PFI6 7 V Start1_PFI7 8 V Start1_PFI8 9 V Start1_PFI9 10 V Start1_RTSI0 11 V Start1_RTSI1 12 V Start1_RTSI2 13 V Start1_RTSI3 14 V Start1_RTSI4 15 V Start1_RTSI5 16 V Start1_RTSI6 17 V Start1_PXIe_DStarA 18 V Start1_PXIe_DStarB 19 V Start1_Star_Trigger 20 V Start1_PFI10 21 V Start1_PFI11 22 V Start1_PFI12 23 V Start1_PFI13 24 V Start1_PFI14 25 V Start1_PFI15 26 V Start1_RTSI7 27 V Start1_DIO_ChgDetect 28 V Start1_Analog_Trigger 30 V Start1_Low 31 V Start1_G0_Out 36 V Start1_G1_Out 37 V Start1_G2_Out 38 V Start1_G3_Out 39 V Start1_DI_Start1 40 V Start1_AO_Start1 43 V Start1_DO_Start1 44 V Start1_IntTriggerA0 53 V Start1_IntTriggerA1 54 V Start1_IntTriggerA2 55 V Start1_IntTriggerA3 56 V Start1_IntTriggerA4 57 V Start1_IntTriggerA5 58 V Start1_IntTriggerA6 59 V Start1_IntTriggerA7 60 #------------------------------------------------------------------------------- # Enumerated type AI_START2_Select_t #------------------------------------------------------------------------------- E AI_START2_Select_t V Start2_SW_Pulse 0 V Start2_PFI0 1 V Start2_PFI1 2 V Start2_PFI2 3 V Start2_PFI3 4 V Start2_PFI4 5 V Start2_PFI5 6 V Start2_PFI6 7 V Start2_PFI7 8 V Start2_PFI8 9 V Start2_PFI9 10 V Start2_RTSI0 11 V Start2_RTSI1 12 V Start2_RTSI2 13 V Start2_RTSI3 14 V Start2_RTSI4 15 V Start2_RTSI5 16 V Start2_RTSI6 17 V Start2_PXIe_DStarA 18 V Start2_PXIe_DStarB 19 V Start2_Star_Trigger 20 V Start2_PFI10 21 V Start2_PFI11 22 V Start2_PFI12 23 V Start2_PFI13 24 V Start2_PFI14 25 V Start2_PFI15 26 V Start2_RTSI7 27 V Start2_DIO_ChgDetect 28 V Start2_Analog_Trigger 30 V Start2_Low 31 V Start2_G0_Out 36 V Start2_G1_Out 37 V Start2_G2_Out 38 V Start2_G3_Out 39 V Start2_DI_Start2 40 V Start2_AO_Start1 43 V Start2_DO_Start1 44 V Start2_IntTriggerA0 53 V Start2_IntTriggerA1 54 V Start2_IntTriggerA2 55 V Start2_IntTriggerA3 56 V Start2_IntTriggerA4 57 V Start2_IntTriggerA5 58 V Start2_IntTriggerA6 59 V Start2_IntTriggerA7 60 #------------------------------------------------------------------------------- # Enumerated type AI_StartConvertSelMux_t #------------------------------------------------------------------------------- E AI_StartConvertSelMux_t V StartCnv_InternalTiming 0 V StartCnv_PFI0 1 V StartCnv_PFI1 2 V StartCnv_PFI2 3 V StartCnv_PFI3 4 V StartCnv_PFI4 5 V StartCnv_PFI5 6 V StartCnv_PFI6 7 V StartCnv_PFI7 8 V StartCnv_PFI8 9 V StartCnv_PFI9 10 V StartCnv_RTSI0 11 V StartCnv_RTSI1 12 V StartCnv_RTSI2 13 V StartCnv_RTSI3 14 V StartCnv_RTSI4 15 V StartCnv_RTSI5 16 V StartCnv_RTSI6 17 V StartCnv_DIO_ChgDetect 18 V StartCnv_G0_Out 19 V StartCnv_Star_Trigger 20 V StartCnv_PFI10 21 V StartCnv_PFI11 22 V StartCnv_PFI12 23 V StartCnv_PFI13 24 V StartCnv_PFI14 25 V StartCnv_PFI15 26 V StartCnv_RTSI7 27 V StartCnv_G1_Out 28 V StartCnv_SCXI_Trig1 29 V StartCnv_Atrig 30 V StartCnv_Low 31 V StartCnv_PXIe_DStarA 32 V StartCnv_PXIe_DStarB 33 V StartCnv_G2_Out 34 V StartCnv_G3_Out 35 V StartCnv_G0_SampleClk 36 V StartCnv_G1_SampleClk 37 V StartCnv_G2_SampleClk 38 V StartCnv_G3_SampleClk 39 V StartCnv_DI_Convert 40 V StartCnv_AO_Update 43 V StartCnv_DO_Update 44 V StartCnv_IntTriggerA0 53 V StartCnv_IntTriggerA1 54 V StartCnv_IntTriggerA2 55 V StartCnv_IntTriggerA3 56 V StartCnv_IntTriggerA4 57 V StartCnv_IntTriggerA5 58 V StartCnv_IntTriggerA6 59 V StartCnv_IntTriggerA7 60 #=============================================================================== # Register Group AI #=============================================================================== #------------------------------------------------------------------------------- # AI_Config_FIFO_Status_Register Register Definition R AI_Config_FIFO_Status_Register 32 0x0 Readable F AI_Config_FIFO_Status 32 @ This bitfield represents the amount of data that remains in the @ AI configuration FIFO. #------------------------------------------------------------------------------- # AI_Data_FIFO_Status_Register Register Definition R AI_Data_FIFO_Status_Register 32 0x4 Readable F AI_Data_FIFO_Status 32 @ This bitfield represents the amount of data that remains in the @ AI data FIFO. #------------------------------------------------------------------------------- # AI_FIFO_Data_Register Register Definition R AI_FIFO_Data_Register 32 0x8 Readable --no-soft-copy true F AI_FIFO_Data 32 @ This bitfield reads from the AI data FIFO via Programmed IO. @

NOTE This register should be read as 32 bits.
@ This register should be used when the AI_FifoWidth is set @ for 4 byte width. Note that the resolution could be any value.

#------------------------------------------------------------------------------- # AI_FIFO_Data_Register16 Register Definition R AI_FIFO_Data_Register16 16 0x8 Readable --no-soft-copy true F AI_FIFO_Data16 16 @ This bitfield reads from the AI data FIFO via Programmed IO. @

NOTE This register should be read as 16 bits.
@ This register should be used when the AI_FifoWidth is set @ for 2 byte width. Note that the resolution should be 16 bits @ or less.

#------------------------------------------------------------------------------- # AI_Config_FIFO_Data_Register Register Definition R AI_Config_FIFO_Data_Register 16 0x1e Writable --force-default true F AI_Config_Channel 4 @ These bits indicate which channel is active for the current resource @ in the scan list. F AI_Config_Bank 2 . nAI::tAI_Config_Bank_t @ These bits indicate which bank is active for the current entry @ in the scan list. F AI_Config_Channel_Type 3 . nAI::tAI_Config_Channel_Type_t @ These bits indicate which type of resource is active for the @ current entry in the scan list. F AI_Config_Gain 3 @ These three bits control the gain settings of the input PGIA @ for the selected analog channel. F Reserved 1 F AI_Config_Dither 1 . nAI::tAI_Disabled_Enabled_t @ This bit enables dithering on the ADC, which improves accuracy F AI_Config_Last_Channel 1 @ This bit should be set in the last entry of the scan sequence @ loaded into the channel configuration memory. F Reserved 1 #------------------------------------------------------------------------------- # AI_Data_Mode_Register Register Definition R AI_Data_Mode_Register 32 0x28 Writable F Reserved 4 F Reserved 3 F AI_DoneNotificationEnable 1 @ This bit enables the generation of the done notification on the @ input stream. This notification happens after a LastShiftIn @ event. After this notification happens, no more data can @ be written until a FIFO reset happens. F AI_FifoWidth 1 . nAI::tAI_FifoWidth_t @

This bitfield allows for selection of the AI FIFO width, @ with a '0' indicating 2 bytes wide, and a '1' indicating 4 @ bytes wide.

Any change to this bitfield must be followed @ by a reset of the AI FIFO (see Reset_Register in AI_Register_pack.vhd). @
This bitfield usually remains constant and @ is based on the resolution of the ADC (2 bytes for 12-, 14-, and @ 16-bits; 4 bytes for 18 and up).
The use of Sentinel @ bits requires a 4 byte FIFO independently of the resolution @ of the ADC.

The extended data is sign-extended for bipolar @ measurements, and it is zero-extended for unipolar measurements. @

The width selected corresponds to the expected @ read size of the direct FIFO data register in programmed IO @ (see ADC_FIFO_Data_Register or ADC_FIFO_Data_Register16). @ Programmed IO reads to the FIFO of different size than the current @ FIFO size are NOT allowed (for example, a 32 bit register @ to a FIFO configured as 16 bits). F Reserved 23 #------------------------------------------------------------------------------- # AI_Trigger_Select_Register Register Definition R AI_Trigger_Select_Register 32 0x2C Writable F AI_START1_Select 6 . nAI::tAI_START1_Select_t @ This bitfield selects the AI_START1 trigger F AI_START1_Edge 1 @ This bit enables edge-sensitive detection of the AI_START1 trigger. @

NOTE Edge detection is required for almost @ all applications. Is is also required when the source of the @ trigger is the SW Pulse

F AI_START1_Polarity 1 . nAI::tAI_Polarity_t @ This bit determines the polarity of the AI_START1 trigger

NOTESet @ this bit to 0 if AI_START1_Select is set to 0 @ (AI_START1_Pulse).

F AI_START2_Select 6 . nAI::tAI_START2_Select_t @ This bitfield selects the AI_START2 trigger F AI_START2_Edge 1 @ This bit enables edge detection of the AI_START2 trigger

NOTE @ Edge detection is required for almost all applications. @ Is is also required when the source of the trigger is @ the SW Pulse

F AI_START2_Polarity 1 . nAI::tAI_Polarity_t @ This bit determines the polarity of AI_START2 trigger

NOTE @ Set this bit to 0 if AI_START2_Select is set to 0 (AI_START2_Pulse).

F AI_External_Gate_Select 6 . nAI::tAI_External_Gate_Select_t @ This bitfield enables and selects the external gate. You can @ use the external gate to pause an analog input operation in @ progress. F Reserved 1 F AI_External_Gate_Polarity 1 . nAI::tAI_Polarity_t @ This bit selects the polarity of the external gate signal F AI_CONVERT_Source_Select 6 . nAI::tAI_StartConvertSelMux_t @ Selects the AI_CONVERT source.
When you set this bitfield @ to 0, the AI Interface is in internal AI_CONVERT mode. When @ you select any other signal as the AI_CONVERT source, the @ AI Timer is in external AI_CONVERT mode. F Reserved 1 F AI_Convert_Source_Polarity 1 . nAI::tAI_Polarity_t @ This bit selects the active edge of the AI_CONVERT source signal. @

NOTE: The polarity of this bit changed from STC @ 2 to STC3. This change was made to make it consistent with @ all other polarity bits.

#------------------------------------------------------------------------------- # AI_Trigger_Select_Register2 Register Definition R AI_Trigger_Select_Register2 32 0x30 Writable F Reserved 16 F AI_START_Select 6 . nAI::tAI_StartConvertSelMux_t @ This bit selects the AI_START trigger.
When you set this @ bit to 0, the AI Timer is in internal AI_START mode. When you @ select any other signal as the AI_START trigger, the AI Timer @ is in external AI_START mode. F AI_START_Edge 1 @ This bit enables edge-sensitive detection of the AI_START trigger. @

NOTE Always set this bit

F AI_START_Polarity 1 . nAI::tAI_Polarity_t @ This bit determines the polarity of AI_START trigger F Reserved 8