// Copyright 2011 National Instruments
// License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT
//   Refer to "MHDDK License Agreement.pdf" in the root of this distribution.

// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// This file is autogenerated!!!
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!

#ifndef ___tDMAController_ipp___
#define ___tDMAController_ipp___

#ifndef ___tDMAController_h___
#include "tDMAController.h"
#endif

#ifndef ___nNIMXRegistermap_tStatus2Ptr_ipp___
#define ___nNIMXRegistermap_tStatus2Ptr_ipp___

typedef nMDBG::tStatus2 nNIMXRegisterMap120_tStatus2;


namespace nNIMXRegisterMap120 {
namespace {

typedef nNIMXRegisterMap120_tStatus2 tStatus2;

inline void setStatus(tStatus2* s, tStatus newStatus)
{
   if (s) s->setCode(newStatus);
}

inline tStatus* toPALStatusPtr(tStatus2* s)
{
   return s ? s->operator tStatus*() : ((tStatus*)NULL);
}

inline tBoolean statusIsFatal(tStatus2* s)
{
   return s && s->isFatal();
}

} // unnamed namespace
} // namespace nNIMXRegisterMap120

#endif // ___nNIMXRegistermap_tStatus2Ptr_ipp___


inline void tDMAController::tReg32IODirect32::write(
   tBusSpaceReference addrSpace,
   u32 offset,
   u32 value,
   nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   addrSpace.write32(offset, value);
}

inline u32 tDMAController::tReg32IODirect32::read(
   tBusSpaceReference addrSpace,
   u32 offset,
   nMDBG::tStatus2* s)
{
   u32 value = (u32)~0;
   if (s && s->isFatal()) return value;
   value = addrSpace.read32(offset);
   return value;
}

inline tBusSpaceReference tDMAController::getBusSpaceReference(void) const
{
   return _addrSpace;
}

inline void tDMAController::setAddressOffset(u32 value, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   _addressOffset = value;
}
inline u32 tDMAController::getAddressOffset(nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return 0UL;
   return _addressOffset;
}
inline tBoolean tDMAController::isDirty(tId id, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return kFalse;
   u32 regId = id&0x01FFFFFF;
   if (regId > kMaxRegisterId) {
      nNIMXRegisterMap120::setStatus(s, kStatusBadSelector);
      return kFalse;
   }

   return _dirtyVector[regId];
}

inline void tDMAController::markDirty(tId id, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   u32 regId = id&0x01FFFFFF;

   if (regId > kMaxRegisterId) {
      nNIMXRegisterMap120::setStatus(s, kStatusBadSelector);
      return;
   }

   _dirtyVector[regId] = 1;
}

inline void tDMAController::markClean(tId id, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   u32 regId = id&0x01FFFFFF;

   if (regId > kMaxRegisterId) {
      nNIMXRegisterMap120::setStatus(s, kStatusBadSelector);
      return;
   }

   _dirtyVector[regId] = 0;
}

inline void tDMAController::markDirty(nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   unsigned int i;
   for (i = 0; i < sizeof(_dirtyVector)/sizeof(_dirtyVector[0]); i++) {
      _dirtyVector[i] = 1;
   }
}

inline void tDMAController::markClean(nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   for (unsigned int i = 0; i < sizeof(_dirtyVector)/sizeof(_dirtyVector[0]); i++) {
      _dirtyVector[i] = 0;
   }
}

inline tDMAController::tChannel_Memory_Address_Register_LSW::tChannel_Memory_Address_Register_LSW()
{
}

inline tDMAController::tChannel_Memory_Address_Register_LSW::tRegisterMap* tDMAController::tChannel_Memory_Address_Register_LSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Memory_Address_Register_LSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline void tDMAController::tChannel_Memory_Address_Register_LSW::writeRegister(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   tIOStrategy::write(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), fieldValue, s);
}

inline u32 tDMAController::tChannel_Memory_Address_Register_LSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline void tDMAController::tChannel_Memory_Address_Register_LSW::writeMemory_Address_LSW(u32 fieldValue, nMDBG::tStatus2* s)
{
   writeRegister((u32(fieldValue) << 0x0) & ~0x0,s);
}
inline u32 tDMAController::tChannel_Memory_Address_Register_LSW::readMemory_Address_LSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x0) >> 0x0);
}

inline tDMAController::tChannel_Memory_Address_Register_MSW::tChannel_Memory_Address_Register_MSW()
{
}

inline tDMAController::tChannel_Memory_Address_Register_MSW::tRegisterMap* tDMAController::tChannel_Memory_Address_Register_MSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Memory_Address_Register_MSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline void tDMAController::tChannel_Memory_Address_Register_MSW::writeRegister(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   tIOStrategy::write(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), fieldValue, s);
}

inline u32 tDMAController::tChannel_Memory_Address_Register_MSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline void tDMAController::tChannel_Memory_Address_Register_MSW::writeMemory_Address_MSW(u32 fieldValue, nMDBG::tStatus2* s)
{
   writeRegister((u32(fieldValue) << 0x0) & ~0x0,s);
}
inline u32 tDMAController::tChannel_Memory_Address_Register_MSW::readMemory_Address_MSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x0) >> 0x0);
}

inline tDMAController::tChannel_Link_Address_Register_LSW::tChannel_Link_Address_Register_LSW()
{
}

inline tDMAController::tChannel_Link_Address_Register_LSW::tRegisterMap* tDMAController::tChannel_Link_Address_Register_LSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Link_Address_Register_LSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline void tDMAController::tChannel_Link_Address_Register_LSW::writeRegister(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   tIOStrategy::write(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), fieldValue, s);
}

inline u32 tDMAController::tChannel_Link_Address_Register_LSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline void tDMAController::tChannel_Link_Address_Register_LSW::writeLink_Address_LSW(u32 fieldValue, nMDBG::tStatus2* s)
{
   writeRegister((u32(fieldValue) << 0x3) & ~0x7,s);
}
inline u32 tDMAController::tChannel_Link_Address_Register_LSW::readLink_Address_LSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x7) >> 0x3);
}

inline tDMAController::tChannel_Link_Address_Register_MSW::tChannel_Link_Address_Register_MSW()
{
}

inline tDMAController::tChannel_Link_Address_Register_MSW::tRegisterMap* tDMAController::tChannel_Link_Address_Register_MSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Link_Address_Register_MSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline void tDMAController::tChannel_Link_Address_Register_MSW::writeRegister(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   tIOStrategy::write(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), fieldValue, s);
}

inline u32 tDMAController::tChannel_Link_Address_Register_MSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline void tDMAController::tChannel_Link_Address_Register_MSW::writeLink_Address_MSW(u32 fieldValue, nMDBG::tStatus2* s)
{
   writeRegister((u32(fieldValue) << 0x0) & ~0x0,s);
}
inline u32 tDMAController::tChannel_Link_Address_Register_MSW::readLink_Address_MSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x0) >> 0x0);
}

inline tDMAController::tChannel_Link_Size_Register::tChannel_Link_Size_Register()
{
}

inline tDMAController::tChannel_Link_Size_Register::tRegisterMap* tDMAController::tChannel_Link_Size_Register::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Link_Size_Register::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline void tDMAController::tChannel_Link_Size_Register::writeRegister(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   tIOStrategy::write(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), fieldValue, s);
}

inline u32 tDMAController::tChannel_Link_Size_Register::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline void tDMAController::tChannel_Link_Size_Register::writeLink_Size(u32 fieldValue, nMDBG::tStatus2* s)
{
   writeRegister((u32(fieldValue) << 0x3) & ~0x7,s);
}
inline u32 tDMAController::tChannel_Link_Size_Register::readLink_Size(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x7) >> 0x3);
}

inline tDMAController::tChannel_Control_Register::tChannel_Control_Register()
{
   _softCopy = u32(0x0);
}

inline tDMAController::tChannel_Control_Register::tRegisterMap* tDMAController::tChannel_Control_Register::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Control_Register::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline tBoolean tDMAController::tChannel_Control_Register::isDirty(nMDBG::tStatus2* s)
{
   return _regMap->isDirty((tDMAController::tId)kId, s);
}

inline void tDMAController::tChannel_Control_Register::markDirty(nMDBG::tStatus2* s)
{
   _regMap->markDirty((tDMAController::tId)kId, s);
}

inline void tDMAController::tChannel_Control_Register::markClean(nMDBG::tStatus2* s)
{
   _regMap->markClean((tDMAController::tId)kId, s);
}

inline tDMAController::tChannel_Control_Register& tDMAController::tChannel_Control_Register::setRegister(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   if (_softCopy != fieldValue) {
      _softCopy = fieldValue;
      markDirty(s);
   }
   return *this;
}

inline u32 tDMAController::tChannel_Control_Register::getRegister(nMDBG::tStatus2*) const
{
   return _softCopy;
}

inline void tDMAController::tChannel_Control_Register::flush(nMDBG::tStatus2* s, tBoolean force)
{
   if (s && s->isFatal()) return;
   if (force || isDirty(s)) {
      tIOStrategy::write(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), _softCopy, s);
      _softCopy &= u32(0xffffffff);
      _softCopy |= u32(0x0);
      markClean(s);
   }
}

inline void tDMAController::tChannel_Control_Register::writeRegister(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   if (s && s->isFatal()) return;
   force = force || (_softCopy != fieldValue);
   _softCopy = fieldValue;
   flush(s, force);
}

inline void tDMAController::tChannel_Control_Register::refresh(nMDBG::tStatus2* s)
{
   _softCopy = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
}

inline u32 tDMAController::tChannel_Control_Register::readRegister(nMDBG::tStatus2* s)
{
   refresh(s);
   return _softCopy;
}

inline tDMAController::tChannel_Control_Register& tDMAController::tChannel_Control_Register::setMODE(nDMAController::tDMA_Mode_t fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   u32 newValue;   newValue = (_softCopy & 0xfffffffc) | ((u32(fieldValue) << 0x0) & ~0xfffffffc);
   setRegister(newValue, s);
   return *this;
}

inline nDMAController::tDMA_Mode_t tDMAController::tChannel_Control_Register::getMODE(nMDBG::tStatus2*) const
{
   return nDMAController::tDMA_Mode_t((_softCopy & ~0xfffffffc) >> 0x0);
}

inline void tDMAController::tChannel_Control_Register::writeMODE(nDMAController::tDMA_Mode_t fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   setMODE(fieldValue, s);
   flush(s, force);
}
inline nDMAController::tDMA_Mode_t tDMAController::tChannel_Control_Register::readMODE(nMDBG::tStatus2* s)
{
   refresh(s);
   return getMODE(s);
}

inline tDMAController::tChannel_Control_Register& tDMAController::tChannel_Control_Register::setNotify_On_Done(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   u32 newValue;   newValue = (_softCopy & 0xffff7fff) | ((u32(fieldValue) << 0xf) & ~0xffff7fff);
   setRegister(newValue, s);
   return *this;
}

inline u32 tDMAController::tChannel_Control_Register::getNotify_On_Done(nMDBG::tStatus2*) const
{
   return u32((_softCopy & ~0xffff7fff) >> 0xf);
}

inline void tDMAController::tChannel_Control_Register::writeNotify_On_Done(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   setNotify_On_Done(fieldValue, s);
   flush(s, force);
}
inline u32 tDMAController::tChannel_Control_Register::readNotify_On_Done(nMDBG::tStatus2* s)
{
   refresh(s);
   return getNotify_On_Done(s);
}

inline tDMAController::tChannel_Control_Register& tDMAController::tChannel_Control_Register::setNotify_On_Total_Count(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   u32 newValue;   newValue = (_softCopy & 0xfdffffff) | ((u32(fieldValue) << 0x19) & ~0xfdffffff);
   setRegister(newValue, s);
   return *this;
}

inline u32 tDMAController::tChannel_Control_Register::getNotify_On_Total_Count(nMDBG::tStatus2*) const
{
   return u32((_softCopy & ~0xfdffffff) >> 0x19);
}

inline void tDMAController::tChannel_Control_Register::writeNotify_On_Total_Count(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   setNotify_On_Total_Count(fieldValue, s);
   flush(s, force);
}
inline u32 tDMAController::tChannel_Control_Register::readNotify_On_Total_Count(nMDBG::tStatus2* s)
{
   refresh(s);
   return getNotify_On_Total_Count(s);
}

inline tDMAController::tChannel_Control_Register& tDMAController::tChannel_Control_Register::setNotify_On_Last_Link(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   u32 newValue;   newValue = (_softCopy & 0xfbffffff) | ((u32(fieldValue) << 0x1a) & ~0xfbffffff);
   setRegister(newValue, s);
   return *this;
}

inline u32 tDMAController::tChannel_Control_Register::getNotify_On_Last_Link(nMDBG::tStatus2*) const
{
   return u32((_softCopy & ~0xfbffffff) >> 0x1a);
}

inline void tDMAController::tChannel_Control_Register::writeNotify_On_Last_Link(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   setNotify_On_Last_Link(fieldValue, s);
   flush(s, force);
}
inline u32 tDMAController::tChannel_Control_Register::readNotify_On_Last_Link(nMDBG::tStatus2* s)
{
   refresh(s);
   return getNotify_On_Last_Link(s);
}

inline tDMAController::tChannel_Control_Register& tDMAController::tChannel_Control_Register::setNotify_On_Error(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   u32 newValue;   newValue = (_softCopy & 0xf7ffffff) | ((u32(fieldValue) << 0x1b) & ~0xf7ffffff);
   setRegister(newValue, s);
   return *this;
}

inline u32 tDMAController::tChannel_Control_Register::getNotify_On_Error(nMDBG::tStatus2*) const
{
   return u32((_softCopy & ~0xf7ffffff) >> 0x1b);
}

inline void tDMAController::tChannel_Control_Register::writeNotify_On_Error(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   setNotify_On_Error(fieldValue, s);
   flush(s, force);
}
inline u32 tDMAController::tChannel_Control_Register::readNotify_On_Error(nMDBG::tStatus2* s)
{
   refresh(s);
   return getNotify_On_Error(s);
}

inline tDMAController::tChannel_Operation_Register::tChannel_Operation_Register()
{
   _softCopy = u32(0x0);
}

inline tDMAController::tChannel_Operation_Register::tRegisterMap* tDMAController::tChannel_Operation_Register::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Operation_Register::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline tBoolean tDMAController::tChannel_Operation_Register::isDirty(nMDBG::tStatus2* s)
{
   return _regMap->isDirty((tDMAController::tId)kId, s);
}

inline void tDMAController::tChannel_Operation_Register::markDirty(nMDBG::tStatus2* s)
{
   _regMap->markDirty((tDMAController::tId)kId, s);
}

inline void tDMAController::tChannel_Operation_Register::markClean(nMDBG::tStatus2* s)
{
   _regMap->markClean((tDMAController::tId)kId, s);
}

inline tDMAController::tChannel_Operation_Register& tDMAController::tChannel_Operation_Register::setRegister(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   if (_softCopy != fieldValue) {
      _softCopy = fieldValue;
      markDirty(s);
   }
   return *this;
}

inline u32 tDMAController::tChannel_Operation_Register::getRegister(nMDBG::tStatus2*) const
{
   return _softCopy;
}

inline void tDMAController::tChannel_Operation_Register::flush(nMDBG::tStatus2* s, tBoolean force)
{
   if (s && s->isFatal()) return;
   if (force || isDirty(s)) {
      tIOStrategy::write(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), _softCopy, s);
      _softCopy &= u32(0xffffffff);
      _softCopy |= u32(0x0);
      markClean(s);
   }
}

inline void tDMAController::tChannel_Operation_Register::writeRegister(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   if (s && s->isFatal()) return;
   force = force || (_softCopy != fieldValue);
   _softCopy = fieldValue;
   flush(s, force);
}

inline void tDMAController::tChannel_Operation_Register::refresh(nMDBG::tStatus2* s)
{
   _softCopy = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
}

inline u32 tDMAController::tChannel_Operation_Register::readRegister(nMDBG::tStatus2* s)
{
   refresh(s);
   return _softCopy;
}

inline tDMAController::tChannel_Operation_Register& tDMAController::tChannel_Operation_Register::setSTART(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   u32 newValue;   newValue = (_softCopy & 0xfffffffe) | ((u32(fieldValue) << 0x0) & ~0xfffffffe);
   setRegister(newValue, s);
   return *this;
}

inline u32 tDMAController::tChannel_Operation_Register::getSTART(nMDBG::tStatus2*) const
{
   return u32((_softCopy & ~0xfffffffe) >> 0x0);
}

inline void tDMAController::tChannel_Operation_Register::writeSTART(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   setSTART(fieldValue, s);
   flush(s, force);
}
inline u32 tDMAController::tChannel_Operation_Register::readSTART(nMDBG::tStatus2* s)
{
   refresh(s);
   return getSTART(s);
}

inline tDMAController::tChannel_Operation_Register& tDMAController::tChannel_Operation_Register::setSTOP(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   u32 newValue;   newValue = (_softCopy & 0xfffffffd) | ((u32(fieldValue) << 0x1) & ~0xfffffffd);
   setRegister(newValue, s);
   return *this;
}

inline u32 tDMAController::tChannel_Operation_Register::getSTOP(nMDBG::tStatus2*) const
{
   return u32((_softCopy & ~0xfffffffd) >> 0x1);
}

inline void tDMAController::tChannel_Operation_Register::writeSTOP(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   setSTOP(fieldValue, s);
   flush(s, force);
}
inline u32 tDMAController::tChannel_Operation_Register::readSTOP(nMDBG::tStatus2* s)
{
   refresh(s);
   return getSTOP(s);
}

inline tDMAController::tChannel_Operation_Register& tDMAController::tChannel_Operation_Register::setCLR_TTC(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   u32 newValue;   newValue = (_softCopy & 0xfffffffb) | ((u32(fieldValue) << 0x2) & ~0xfffffffb);
   setRegister(newValue, s);
   return *this;
}

inline u32 tDMAController::tChannel_Operation_Register::getCLR_TTC(nMDBG::tStatus2*) const
{
   return u32((_softCopy & ~0xfffffffb) >> 0x2);
}

inline void tDMAController::tChannel_Operation_Register::writeCLR_TTC(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   setCLR_TTC(fieldValue, s);
   flush(s, force);
}
inline u32 tDMAController::tChannel_Operation_Register::readCLR_TTC(nMDBG::tStatus2* s)
{
   refresh(s);
   return getCLR_TTC(s);
}

inline tDMAController::tChannel_Operation_Register& tDMAController::tChannel_Operation_Register::setArm_Total_Count_Int(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return *this;
   u32 newValue;   newValue = (_softCopy & 0xfdffffff) | ((u32(fieldValue) << 0x19) & ~0xfdffffff);
   setRegister(newValue, s);
   return *this;
}

inline u32 tDMAController::tChannel_Operation_Register::getArm_Total_Count_Int(nMDBG::tStatus2*) const
{
   return u32((_softCopy & ~0xfdffffff) >> 0x19);
}

inline void tDMAController::tChannel_Operation_Register::writeArm_Total_Count_Int(u32 fieldValue, nMDBG::tStatus2* s, tBoolean force)
{
   setArm_Total_Count_Int(fieldValue, s);
   flush(s, force);
}
inline u32 tDMAController::tChannel_Operation_Register::readArm_Total_Count_Int(nMDBG::tStatus2* s)
{
   refresh(s);
   return getArm_Total_Count_Int(s);
}

inline tDMAController::tChannel_Status_Register::tChannel_Status_Register()
{
}

inline tDMAController::tChannel_Status_Register::tRegisterMap* tDMAController::tChannel_Status_Register::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Status_Register::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline u32 tDMAController::tChannel_Status_Register::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline u32 tDMAController::tChannel_Status_Register::readSTREAM(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xfffff000) >> 0x0);
}

inline u32 tDMAController::tChannel_Status_Register::readLink_Ready(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xffffbfff) >> 0xe);
}

inline u32 tDMAController::tChannel_Status_Register::readDone(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xffff7fff) >> 0xf);
}

inline u32 tDMAController::tChannel_Status_Register::readTotal_Count(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xfdffffff) >> 0x19);
}

inline u32 tDMAController::tChannel_Status_Register::readLast_Link(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xfbffffff) >> 0x1a);
}

inline u32 tDMAController::tChannel_Status_Register::readError(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xf7ffffff) >> 0x1b);
}

inline u32 tDMAController::tChannel_Status_Register::readAdditional_Int(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xbfffffff) >> 0x1e);
}

inline u32 tDMAController::tChannel_Status_Register::readInt(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x7fffffff) >> 0x1f);
}

inline tDMAController::tChannel_Volatile_Status_Register::tChannel_Volatile_Status_Register()
{
}

inline tDMAController::tChannel_Volatile_Status_Register::tRegisterMap* tDMAController::tChannel_Volatile_Status_Register::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Volatile_Status_Register::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline u32 tDMAController::tChannel_Volatile_Status_Register::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline u32 tDMAController::tChannel_Volatile_Status_Register::readVol_STREAM(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xfffff000) >> 0x0);
}

inline u32 tDMAController::tChannel_Volatile_Status_Register::readVol_Link_Ready(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xffffbfff) >> 0xe);
}

inline u32 tDMAController::tChannel_Volatile_Status_Register::readVol_Done(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xffff7fff) >> 0xf);
}

inline u32 tDMAController::tChannel_Volatile_Status_Register::readVol_Total_Count(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xfdffffff) >> 0x19);
}

inline u32 tDMAController::tChannel_Volatile_Status_Register::readVol_Last_Link(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xfbffffff) >> 0x1a);
}

inline u32 tDMAController::tChannel_Volatile_Status_Register::readVol_Error(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xf7ffffff) >> 0x1b);
}

inline u32 tDMAController::tChannel_Volatile_Status_Register::readVol_Additional_Int(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0xbfffffff) >> 0x1e);
}

inline u32 tDMAController::tChannel_Volatile_Status_Register::readVol_Int(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x7fffffff) >> 0x1f);
}

inline tDMAController::tChannel_Total_Transfer_Count_Compare_Register_LSW::tChannel_Total_Transfer_Count_Compare_Register_LSW()
{
}

inline tDMAController::tChannel_Total_Transfer_Count_Compare_Register_LSW::tRegisterMap* tDMAController::tChannel_Total_Transfer_Count_Compare_Register_LSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Compare_Register_LSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Compare_Register_LSW::writeRegister(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   tIOStrategy::write(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), fieldValue, s);
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Compare_Register_LSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Compare_Register_LSW::writeTCC_LSW(u32 fieldValue, nMDBG::tStatus2* s)
{
   writeRegister((u32(fieldValue) << 0x0) & ~0x0,s);
}
inline u32 tDMAController::tChannel_Total_Transfer_Count_Compare_Register_LSW::readTCC_LSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x0) >> 0x0);
}

inline tDMAController::tChannel_Total_Transfer_Count_Compare_Register_MSW::tChannel_Total_Transfer_Count_Compare_Register_MSW()
{
}

inline tDMAController::tChannel_Total_Transfer_Count_Compare_Register_MSW::tRegisterMap* tDMAController::tChannel_Total_Transfer_Count_Compare_Register_MSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Compare_Register_MSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Compare_Register_MSW::writeRegister(u32 fieldValue, nMDBG::tStatus2* s)
{
   if (s && s->isFatal()) return;
   tIOStrategy::write(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), fieldValue, s);
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Compare_Register_MSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Compare_Register_MSW::writeTCC_MSW(u32 fieldValue, nMDBG::tStatus2* s)
{
   writeRegister((u32(fieldValue) << 0x0) & ~0x0,s);
}
inline u32 tDMAController::tChannel_Total_Transfer_Count_Compare_Register_MSW::readTCC_MSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x0) >> 0x0);
}

inline tDMAController::tChannel_Total_Transfer_Count_Status_Register_LSW::tChannel_Total_Transfer_Count_Status_Register_LSW()
{
}

inline tDMAController::tChannel_Total_Transfer_Count_Status_Register_LSW::tRegisterMap* tDMAController::tChannel_Total_Transfer_Count_Status_Register_LSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Status_Register_LSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Status_Register_LSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Status_Register_LSW::readTTCS_LSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x0) >> 0x0);
}

inline tDMAController::tChannel_Total_Transfer_Count_Status_Register_MSW::tChannel_Total_Transfer_Count_Status_Register_MSW()
{
}

inline tDMAController::tChannel_Total_Transfer_Count_Status_Register_MSW::tRegisterMap* tDMAController::tChannel_Total_Transfer_Count_Status_Register_MSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Status_Register_MSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Status_Register_MSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Status_Register_MSW::readTTCS_MSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x0) >> 0x0);
}

inline tDMAController::tChannel_Total_Transfer_Count_Latching_Register_LSW::tChannel_Total_Transfer_Count_Latching_Register_LSW()
{
}

inline tDMAController::tChannel_Total_Transfer_Count_Latching_Register_LSW::tRegisterMap* tDMAController::tChannel_Total_Transfer_Count_Latching_Register_LSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Latching_Register_LSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Latching_Register_LSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Latching_Register_LSW::readTTCL_LSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x0) >> 0x0);
}

inline tDMAController::tChannel_Total_Transfer_Count_Latching_Register_MSW::tChannel_Total_Transfer_Count_Latching_Register_MSW()
{
}

inline tDMAController::tChannel_Total_Transfer_Count_Latching_Register_MSW::tRegisterMap* tDMAController::tChannel_Total_Transfer_Count_Latching_Register_MSW::registerMap(void)
{
   return _regMap;
}

inline void tDMAController::tChannel_Total_Transfer_Count_Latching_Register_MSW::setRegisterMap(tRegisterMap* pRegMap)
{
   _regMap = pRegMap;
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Latching_Register_MSW::readRegister(nMDBG::tStatus2* s)
{
   u32 fieldValue;
   fieldValue = tIOStrategy::read(_regMap->getBusSpaceReference(), kOffset + _regMap->getAddressOffset(s), s);
   return fieldValue;
}

inline u32 tDMAController::tChannel_Total_Transfer_Count_Latching_Register_MSW::readTTCL_MSW(nMDBG::tStatus2* s)
{
   u32 value = readRegister(s);
   return u32((value & ~0x0) >> 0x0);
}

#endif


// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!
// This file is autogenerated!!!
// !!!!!!!!!!!!!!!!!!!!!!!!!!!!!